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Solid electrolyte switching device, FPGA using same, memory device, and method for manufacturing solid electrolyte switching device

外国特許コード F110005236
整理番号 B01-01WO
掲載日 2011年8月29日
出願国 アメリカ合衆国
出願番号 51257103
公報番号 20050127524
公報番号 7750332
出願日 平成15年4月25日(2003.4.25)
公報発行日 平成17年6月16日(2005.6.16)
公報発行日 平成22年7月6日(2010.7.6)
国際出願番号 JP2003005393
国際公開番号 WO2003094227
国際出願日 平成15年4月25日(2003.4.25)
国際公開日 平成15年11月13日(2003.11.13)
優先権データ
  • 特願2002-129283 (2002.4.30) JP
  • 特願2002-346129 (2002.11.28) JP
  • 2003WO-JP05393 (2003.4.25) WO
発明の名称 （英語） Solid electrolyte switching device, FPGA using same, memory device, and method for manufacturing solid electrolyte switching device
発明の概要（英語） (US7750332)
The present invention provides a solid electrolyte switching device, which can maintain an on or off state when the power source is removed, the resistance of which in on the state is low, and which is capable of integration and re-programming, and FPGA and a memory device using the same, and a method of manufacturing the same.
A solid electrolyte switching device (10, 10′, 20, 20′) comprises a substrate (11) in which surface is coated with an insulation layer, a first interconnection layer (13) set on said substrate (11), an ion supplying layer (17) set on said first interconnection layer (13), a solid electrolyte layer (16) set on said ion supplying layer (17), an interlevel insulating layer (12) having a via hole set to cover said first interconnection layer (13), said ion supplying layer (17), and said solid electrolyte layer (16), a counter electrode layer (15) set to contact said solid electrolyte layer (16) through the via hole of said interlevel insulating layer (12), and a second interconnection layer (14) set to cover said counter electrode layer (15).
The switching device can be provided in which the on state, or the off state can be arbitrarily set by the threshold voltage applied between the ion supplying layer (17) and the counter electrode layer (15), which is non-volatile, and the resistance of which in the on state is low.
The switching device of the present invention is also simple and fine in structure, and hence makes it possible to provide smaller switching devices than are currently available.
Further, using the switching device of the present invention as the switching device of an FPGA (30) makes it possible to provide re-programmable and fast operation FPGA (30).
Using the switching device of the present invention as a memory cell of a memory device makes it possible to provide a non-volatile memory device with high programming and reading speed.
特許請求の範囲（英語） [claim1]
1. A solid electrolyte switching device, comprising: a substrate in which a surface is coated with an insulation layer;
a first interconnection layer set on said substrate;
an ion supplying layer set on said first interconnection layer;
a solid electrolyte layer set on said ion supplying layer;
an interlevel insulating layer having a via hole set to cover said first interconnection layer, said ion supplying layer, and said solid electrolyte layer;
a counter electrode layer set to contact said solid electrolyte layer through said via hole of said interlevel insulating layer; and
a second interconnection layer set to cover said counter electrode layer,
wherein said first interconnection layer is formed with the same material as that of said ion supplying layer,
said via hole is confined in area so that said interlevel insulating layer contacts an outer periphery of a top surface of said solid electrolyte layer and said counter electrode layer contacts an area inside of the outer periphery of the top surface of said solid electrolyte layer, and
said solid electrolyte layer is any one of chromium sulfide, titanium sulfide, tungsten sulfide, nickel sulfide, tantalum sulfide, molybdenum sulfide, germanium-antimony-tellurium compound, and arsenic-tellurium-germanium-silicon compound.
[claim2]
2. A solid electrolyte switching device, comprising: a substrate in which a surface is coated with an insulation layer;
a first interconnection layer set on said substrate;
an ion supplying layer set on said first interconnection layer;
a solid electrolyte layer set on said ion supplying layer;
an interlevel insulating layer having a via hole set to cover said first interconnection layer, said ion supplying layer, and said solid electrolyte layer;
a counter electrode layer set to contact with an outer region of said solid electrolyte layer through said via hole of said interlevel insulating layer; and
a second interconnection layer set to cover said counter electrode layer,
wherein said interlevel insulating layer is sandwiched between said substrate and said second interconnection layer and is in contact with each of said counter electrode layer, said first interconnection layer, said ion supplying layer, and said solid electrolyte layer,
said via hole is confined in area so that said interlevel insulating layer contacts an outer periphery of a top surface of said solid electrolyte layer and said counter electrode layer contacts an area inside of the outer periphery of the top surface of said solid electrolyte layer, and
said solid electrolyte layer is any one of chromium sulfide, titanium sulfide, tungsten sulfide, nickel sulfide, tantalum sulfide, molybdenum sulfide, germanium-antimony-tellurium compound, and arsenic-tellurium-germanium-silicon compound.
[claim3]
3. The solid electrolyte switching device as set forth in claim 1 or claim 2, characterized in that said solid electrolyte layer consists of an ion conductive material, and said ion supplying layer consists of the material which supplies ions to said ion conductive material.
[claim4]
4. The solid electrolyte switching device as set forth in claim 1 or claim 2, characterized in that said ion supplying layer is copper.
[claim5]
5. The solid electrolyte switching device as set forth in claim 1 or claim 2, characterized in that said solid electrolyte layer consists of the mixed conductive material in which ion conduction and electron conduction co-exist, and said ion supplying layer consists of the material which supplies ions to said mixed conductive material.
[claim6]
6. The solid electrolyte switching device as set forth in claim 1 or claim 2, characterized in that the combination of said solid electrolyte layer and said ion supplying layer is any one combination of chromium sulfide and chromium, titanium sulfide and titanium, tungsten sulfide and tungsten, nickel sulfide and nickel, and tantalum sulfide and tantalum.
[claim7]
7. The solid electrolyte switching device as set forth in claim 1 or claim 2, characterized in that said counter electrode layer is any one of platinum, aluminum, copper, titanium, tungsten, vanadium, niobium, tantalum, chromium, molybdenum, and the nitride or silicide of these metals, or the combination thereof.
[claim8]
8. The solid electrolyte switching device as set forth in claim 1 or claim 2, characterized in that, said solid electrolyte switching device has off characteristics in the initial state before voltage application.
[claim9]
9. The solid electrolyte switching device as set forth in claim 1 or claim 2, characterized in that said solid electrolyte switching device has on characteristics in the initial state before voltage application.
[claim10]
10. FPGA which uses a solid electrolyte switching device, characterized in that the solid electrolyte switching device as set forth in claim 1 is used as a switching device for programming of FPGA.
[claim11]
11. A memory device which uses a solid electrolyte switching device, characterized in that said memory device has the solid electrolyte switching device as set forth in claim 1, and a MOS transistor, and said first or second interconnection layer of said solid electrolyte switching device is connected to the drain or source of said MOS transistor.
[claim12]
12. A memory device which uses a solid electrolyte switching device, characterized in that said memory cell has the solid electrolyte switching device as set forth in claim 1, and a MOS transistor, and the first interconnection layer of said solid electrolyte switching device is connected to the drain of said MOS transistor, and the second interconnection layer of said solid electrolyte switching device is connected to a ground line, and the source of said MOS transistor is made an address line, and the gate of said MOS transistor is made a word line.
[claim13]
13. The solid electrolyte switching device as set forth in claim 1, wherein said interlevel insulating layer is sandwiched between said substrate and said second interconnection layer and is in contact with each of said counter electrode layer, said first interconnection layer, said ion supplying layer, and said solid electrolyte layer.
[claim14]
14. The solid electrolyte switching device as set forth in claim 1, wherein a current voltage characteristic of said solid electrolyte switching device is caused by a current path formed inside said solid electrolyte layer.
[claim15]
15. The solid electrolyte switching device as set forth in claim 1, wherein said ion supplying layer is of copper and said counter electrode layer is of titanium, and wherein a current voltage characteristic of said solid electrolyte switching device is caused by a current path formed inside said solid electrolyte layer.
[claim16]
16. The solid electrolyte switching device as set forth in claim 2, wherein a current voltage characteristic of said solid electrolyte switching device is caused by a current path formed inside said solid electrolyte layer.
[claim17]
17. The solid electrolyte switching device as set forth in claim 2, wherein said ion supplying layer is of copper and said counter electrode layer is of titanium, and wherein a current voltage characteristic of said solid electrolyte switching device is caused by a current path formed inside said solid electrolyte layer.
  • 発明者/出願人（英語）
  • SAKAMOTO TOSHITSUGU
  • AONO MASAKAZU
  • HASEGAWA TSUYOSHI
  • NAKAYAMA TOMONOBU
  • SUNAMURA HIROSHI
  • KAWAURA HISAO
  • SUGIBAYASHI NAOHIKO
  • JAPAN SCIENCE AND TECHNOLOGY AGENCY
  • NEC
  • RIKEN
国際特許分類(IPC)
参考情報 （研究プロジェクト等） SORST Selected in Fiscal 2000

日本語項目の表示

発明の名称 固体電解質スイッチング素子及びそれを用いたＦＰＧＡ、メモリ素子、並びに固体電解質スイッチング素子の製造方法
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  • FAX: 03-5214-8476

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『 Solid electrolyte switching device, FPGA using same, memory device, and method for manufacturing solid electrolyte switching device 』に関するお問合せ


  • 国立研究開発法人科学技術振興機構（ＪＳＴ） 知的財産マネジメント推進部
  • URL: http://www.jst.go.jp/chizai/
  • E-mail: e-mail address
  • Address: 〒102-8666 東京都千代田区四番町5-3
  • TEL: 03-5214-8293
  • FAX: 03-5214-8476

お問合せ

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公報 20050127524(PDF,347KB) PDF
公報 7750332(PDF,354KB) PDF
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