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Field effect transistor and method for manufacturing same meetings

Foreign code F110005385
File No. K02011WO
Posted date Sep 5, 2011
Country United States of America
Application number 56562404
Gazette No. 20060194379
Gazette No. 7622763
Date of filing Jul 28, 2004
Gazette Date Aug 31, 2006
Gazette Date Nov 24, 2009
International application number JP2004010696
International publication number WO2005010974
Date of international filing Jul 28, 2004
Date of international publication Feb 3, 2005
Priority data
  • P2003-281104 (Jul 28, 2003) JP
  • 2004WO-JP10696 (Jul 28, 2004) WO
Title Field effect transistor and method for manufacturing same meetings
Abstract (US7622763)
A field effect transistor comprises a SiC substrate 1, a source 3a and a drain 3b formed on the surface of the SiC substrate 1, an insulating structure comprising an AlN layer 5 formed in contact with the SiC surface and having a thickness of one molecule-layer or greater, and a SiO2 layer formed thereon, and a gate electrode 15 formed on the insulation structure.
Leakage current can be controlled while the state of interface with SiC is maintained in a good condition.
Scope of claims [claim1]
1. A non-volatile memory element comprising: an SiC surface structure;
a floating-gate structure formed on said SiC surface structure, wherein said floating-gate structure includes an interface control layer, a first insulator barrier layer, a floating-gate layer formed of a metal or a semiconductor quantum well, a second insulator barrier layer, and a gate electrode layer, wherein said interface control layer is a Group-III nitride layer formed in contact with said SiC surface structure and having a film thickness in the range of one molecule-layer to a critical film thickness such that no misfit dislocation occurs with said SiC surface structure; and
a source and a drain formed on said SiC surface structure adjacent to said floating-gate structure.
[claim2]
2. The nonvolatile memory element according to claim 1, wherein said interface control layer is AlN having a thickness of 6 nm or smaller.
[claim3]
3. The field effect transistor according to claim 1, wherein said first insulator barrier layer has a double-layered film structure on said interface control layer, said double-layered film structure comprising an Al2O3 layer and a SiO2 layer layered in order.
[claim4]
4. The nonvolatile memory element according to claim 1, wherein said first insulator barrier layer comprises a layer formed from a material that is different from said interface control layer and that has a greater band offset with respect to a conduction carrier than said interface control layer.
[claim5]
5. The field effect transistor according to claim 2, wherein said first insulator barrier layer has a double-layered film structure on said interface control layer, said double-layered film structure comprising an Al2O3 layer and a SiO2 layer layered in order.
[claim6]
6. A nonvolatile memory element comprising: an SiC surface structure;
a floating-gate structure formed on said SiC surface structure including a first insulator barrier layer, a well layer, a second insulator barrier layer, and a gate electrode layer, wherein said first insulator barrier layer is formed in contact with said SiC surface structure and comprises a Group-III nitride epitaxial layer, said well layer is formed of a Group-III nitride epitaxial layer and functions as a floating gate, and said second insulator barrier layer is formed of a Group-III nitride epitaxial layer; and
a source and a drain formed in said SiC surface structure adjacent to said floating-gate structure.
[claim7]
7. The nonvolatile memory element according to claim 6, wherein said first insulator barrier layer is a Group-III nitride layer that has a film thickness in the range of one molecule-layer to a critical film thickness such that no misfit dislocation with said SiC surface structure occurs.
[claim8]
8. The nonvolatile memory element according to claim 6, wherein said first insulator barrier layer is a layer comprised of AlN and having a thickness of one molecule-layer or greater to 6 nm or smaller.
[claim9]
9. The nonvolatile memory element according to claim 6, wherein said well layer contains Ga and N.
[claim10]
10. The nonvolatile memory element according to claim 6, wherein said second insulator barrier layer contains Al and N.
  • Inventor, and Inventor/Applicant
  • SUDA JUN
  • MATSUNAMI HIROYUKI
  • JAPAN SCIENCE AND TECHNOLOGY AGENCY
IPC(International Patent Classification)
Reference ( R and D project ) PRESTO Nanostructure and Material Property AREA
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