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Optically reconfigurable logic circuit

Foreign code F110005597
File No. RSP53P16WO
Posted date Sep 9, 2011
Country United States of America
Application number 59747405
Gazette No. 20090296178
Gazette No. 07876483
Date of filing May 11, 2005
Gazette Date Dec 3, 2009
Gazette Date Jan 25, 2011
International application number PCT/JP2005/008612
International publication number WO2005/117262
Date of international filing May 11, 2005
Date of international publication Dec 8, 2005
Priority data
  • P2004-156769 (May 26, 2004) JP
Title Optically reconfigurable logic circuit
Abstract To provide an optically reconfigurable logic circuit in which a mount area of an optical circuit is reduced as much as possible and a high gate density is realized.In an optically reconfigurable logic circuit 1 provided with a plurality of configuration information input circuits 6 for converting an optical signal including logic circuit configuration information into an electric signal and holding and outputting this electric signal and a logic configuration variable circuit 7 for performing logic configuration on the basis of the logic circuit configuration information, the configuration information input circuits 6 holds the logic circuit configuration information as electric charge with use of a junction capacitance and a floating capacitance of a photoconductive device P. An inter-terminal voltage of the photoconductive device P is converted into binary data by a binary circuit and output as a circuit configuration signal. Then, the logic configuration variable circuit 7 is configured to execute a logic arithmetic processing before the inter-terminal voltage of the photoconductive device P drops to be equal to or lower than a logic threshold of the binary circuit due to a leak current.
  • Inventor, and Inventor/Applicant
  • Watanabe, Minoru; Iizuka [JP]
  • Kobayashi, Fuminori; Munakata [JP]
  • Japan Science and Technology Agency, Kawaguchi-shi [JP]
IPC(International Patent Classification)
U.S. Cl./(Sub)
  • 359/108
  • 257/202
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