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Impedance matching circuit, and semiconductor element and radio communication device using the same UPDATE

外国特許コード F110005629
整理番号 RX05P01WO
掲載日 2011年9月9日
出願国 アメリカ合衆国
出願番号 54875804
公報番号 20060170515
公報番号 7498897
出願日 平成16年3月4日(2004.3.4)
公報発行日 平成18年8月3日(2006.8.3)
公報発行日 平成21年3月3日(2009.3.3)
国際出願番号 JP2004002751
国際公開番号 WO2004082064
国際出願日 平成16年3月4日(2004.3.4)
国際公開日 平成16年9月23日(2004.9.23)
優先権データ
  • 特願2003-064128 (2003.3.10) JP
  • 2004WO-JP02751 (2004.3.4) WO
発明の名称 (英語) Impedance matching circuit, and semiconductor element and radio communication device using the same UPDATE
発明の概要(英語) (US7498897)
An impedance matching circuit, a semiconductor element and a radio communication device using the same, adjusting bandwidth while permitting it to be constructed on the semiconductor element by reducing its occupation area.
Since a reactance compensating distributed constant line (31) compensates reactance (BL, XS) of a load (6) and a quarter-wave transmission line (32) and an impedance inverting distributed constant line (33) composing an impedance inverting circuit (K inverter or J inverter) corresponding to the degree of impedance (ZL, ZS) of the load (6) match the impedance (ZL, ZS) of the compensated load (6) and output the input signals (SI1, SI2) at the preset bandwidth, adjustment of bandwidth can be made while miniaturizing the impedance matching circuit (7a) by shortening the line length of the reactance compensating distributed constant line (31) and the quarter-wave transmission line (32).
特許請求の範囲(英語) [claim1]
1. An impedance matching circuit comprising a distributed constant line (i) constructed on a dielectric substrate and (ii) operable to output an input signal having a preset bandwidth, wherein said distributed constant line comprises: a reactance compensating distributed constant line (i) connected to a load and (ii) having a line length of a length compensating reactance of said load;
a quarter-wave distributed constant line (i) connected to said reactance compensating distributed constant line, (ii) having a line length of a quarter wavelength of said input signal and (iii) having a characteristic impedance that is set to correspond to said preset bandwidth;
and
an impedance inverting distributed constant line (i) connected to said quarter-wave distributed constant line and (ii) including an impedance inverting circuit that corresponds to a degree of impedance of said load and that includes one of a K inverter and a J inverter selectively corresponding to said preset bandwidth,wherein said impedance inverting distributed constant line satisfies Z1=(pi /4) * [w/(g1 * g2 * GL)], andwherein Z1 is the characteristic impedance that is set to correspond to the preset bandwidth, w is the preset bandwidth, g1 and g2 are normalized element values and GL is the conductance of the load.
[claim2]
2. The impedance matching circuit as set forth in claim 1, wherein said distributed constant line further comprises a narrow band pass distributed constant line including a resonance circuit having a line length of the quarter wavelength of said input signal and including an impedance inverting circuit including the K inverter and the J inverter, the J inverter being adjacent to the K inverter and being connected to the K inverter via said resonance circuit.
[claim3]
3. The impedance matching circuit as set forth in claim 1, wherein said reactance compensating distributed constant line, said quarter-wave distributed constant line and said impedance inverting distributed constant line are comprised of ground conductors and a signal line formed on one face of said dielectric substrate.
[claim4]
4. The impedance matching circuit as set forth in claim 3, wherein a signal line of at least said quarter-wave distributed constant line from among signal lines of said reactance compensating distributed constant line and said quarter-wave distributed constant line meanders.
[claim5]
5. A semiconductor element comprising the impedance matching circuit as set forth in claim 1.
[claim6]
6. A radio communication device comprising the semiconductor element as set forth in claim 5 and an antenna connected to said semiconductor element.
  • 発明者/出願人(英語)
  • YOSHIDA KEIJI
  • KANAYA HARUICHI
  • TSUCHIYA TADAAKI
  • JAPAN SCIENCE AND TECHNOLOGY AGENCY
  • LOGIC RESEARCH
国際特許分類(IPC)
米国特許分類/主・副
  • H01P005/02
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