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Optically reconfigurable gate array write state inspection method, write state inspection device, and optically reconfigurable gate array

外国特許コード F110005630
整理番号 RX05P10WO
掲載日 2011年9月9日
出願国 アメリカ合衆国
出願番号 62975005
公報番号 20080030225
公報番号 7508234
出願日 平成17年6月16日(2005.6.16)
公報発行日 平成20年2月7日(2008.2.7)
公報発行日 平成21年3月24日(2009.3.24)
国際出願番号 JP2005011026
国際公開番号 WO2005125013
国際出願日 平成17年6月16日(2005.6.16)
国際公開日 平成17年12月29日(2005.12.29)
優先権データ
  • 特願2004-181913 (2004.6.18) JP
  • 2005WO-JP11026 (2005.6.16) WO
発明の名称 (英語) Optically reconfigurable gate array write state inspection method, write state inspection device, and optically reconfigurable gate array
発明の概要(英語) (US7508234)
A technology for inspecting a write state without requiring a dedicated circuit for write state inspection of a local circuit in an ORGA.
Upon switching an optical signal to be irradiated on an optically reconfigurable bit element as an inspection target from ON to OFF, in the logical circuit structure of the ORGA, first and second optical signal patterns having the optical signal ON/OFF to be irradiated to the optically reconfigurable bit element serving as optical signal patterns configuring the logical structure in which at least one logical level or output impedance changes are sequentially irradiated and input to the logical circuit.
In addition, an output-state detection circuit that is connected to the logical output terminals and detects whether the logical level of the output terminal is at an H level, L level, or high impedance detects the output state.
特許請求の範囲(英語) [claim1]
1. A write state inspection method of an optically reconfigurable gate array, the optically reconfigurable gate array including a logical circuit chip having a logical circuit having a plurality of optically reconfigurable bit elements and enabling the reconfiguration of the logical structure of the logical circuit by reading a desired optical signal pattern stored in an optical memory and irradiating a logical circuit chip with an optical signal, the write state inspection method for inspecting an information write state of the optically reconfigurable bit element with the optical signal, comprising: a first step of configuring, to the logical circuit, a logical structure (hereinafter, a "logical circuit for inspection") for inspecting the optically reconfigurable bit element by irradiating an optical signal pattern for inspection (hereinafter, referred to as an "inspection pattern") stored in advance to the optical memory to the logical circuit chip;
a second step of detecting whether an output state of an output terminal of the logical circuit chip to the logical circuit for inspection is a state of the logical level as the H level, the logical level as the L level, or the output impedance as high impedance;
and
a third step of judging, by comparing the detected state with the normal output state of the logical circuit for inspection, whether the information write state of the optically reconfigurable bit element with the optical signal is successful or unsuccessful,wherein the inspection pattern includes a first inspection pattern in which the optical signal irradiated to the optically reconfigurable bit element as an inspection target is in an OFF-state and a second inspection pattern in which the optical signal irradiated to the optically reconfigurable bit element as the inspection target is in an ON-state, andthe first step to third step are executed by sequentially irradiating the first and second inspection patterns in order of the two inspection patterns or inverse order.
[claim2]
2. The write state inspection method according to claim 1, wherein the logical circuit for inspection has a logical structure in which the output of the output terminal of the logical circuit chip changes depending on an input of the optical signal to the optically reconfigurable bit element as the inspection target.
[claim3]
3. The write state inspection method according to claim 1, wherein the logical circuit for inspection has a logical structure in which the output of the output terminal of the logical circuit chip changes depending on the input of the optical signal to the optically reconfigurable bit element and does not depend on the input of the optical signal to the optically reconfigurable bit element whose inspection of the write state does not end yet.
[claim4]
4. A write state inspection device of an optically reconfigurable gate array, the optically reconfigurable gate array including a logical circuit chip having a logical circuit having a plurality of optically reconfigurable bit elements and enabling the reconfiguration of the logical structure of the logical circuit by reading a desired optical signal pattern stored in an optical memory and irradiating a logical circuit chip with an optical signal, the write state inspection device for inspecting an information write state of the optically reconfigurable bit element with the optical signal comprising: the optical memory that stores an optical signal pattern for inspection (hereinafter, "inspection pattern") for configuring a logical structure (hereinafter, "logical circuit for inspection") for inspecting the optically reconfigurable bit element to the logical circuit;
inspection-signal input means that reads the inspection pattern stored in the optical memory as an optical signal pattern and irradiates the logical circuit chip;
and
output-state detection means that detects whether the output state of an output terminal of the logical circuit chip is the logical level as the H level, logical level as the L level, or output impedance as high impedance,wherein the optical memory stores a first inspection pattern in which the optical signal irradiated to the optically reconfigurable bit element as an inspection target is in the OFF-state and a second inspection pattern in which the optical signal irradiated to the optically reconfigurable bit element as the inspection target is in the ON-state,the inspection-signal input means sequentially irradiates the first and second inspection patterns in order of the two inspection patterns or inverse order, andthe output-state detection means detects, for the inspection patterns, whether the output state of the output terminal of the logical circuit chip is the logical level as the H level, logical level as the level, or output impedance as high impedance.
[claim5]
5. The write state inspection device according to claim 4, further comprising: output-state judgment means that judges, by comparing the output state of the output terminal of the logical circuit chip of the logical circuit for inspection detected by the output state detection circuit with a normal output state of the logical circuit for inspection, whether the information write state of the optically reconfigurable bit element with the optical signal is successful or unsuccessful.
[claim6]
6. The write state inspection device according to claim 4, wherein the logical circuit for inspection has a logical structure in which the output of the output terminal of the logical circuit chip changes depending on the input of the optical signal to the optically reconfigurable bit element as an inspection target.
[claim7]
7. The write state inspection device according to claim 4, wherein the output-state detection means comprises: a voltage detection circuit that detects a voltage of the output terminal of the logical circuit;
and
a detection voltage applying circuit that switchably applies a voltage not less than a logical threshold or voltage not more than the logical threshold to the output terminal of the logical circuit via a resistor.
[claim8]
8. An optically reconfigurable gate array including a logical circuit chip having a logical circuit having a plurality of optically reconfigurable bit elements and enabling the reconfiguration of a logical structure of the logical circuit by reading a desired optical signal pattern stored in an optical memory and irradiating the logical circuit chip with an optical signal, the optically reconfigurable gate array comprising: an output-state detection circuit that is connected to an output terminal of the logical circuit chip and detects the logical level of the output terminal as the H level state, the logical level of the output terminal as the L level state, or the output impedance of the output terminal as the high impedance state,wherein the logical circuit mounted on the logical circuit chip comprises:an optically reconfigurable logical block having an optically reconfigurable logical circuit having a plurality of optically reconfigurable bit elements for reconfiguring the logical structure;an optically reconfigurable connecting circuit serving as a connecting circuit for switching wiring connection of a logical signal input/output to the optically reconfigurable logical block, having a plurality of the optically reconfigurable bit elements that reconfigure the connecting structure thereof;
and
an optically reconfigurable input/output circuit, serving as an input/output circuit for switching the connection between an input/output terminal and the wiring, having a plurality of the optically reconfigurable bit elements for reconfiguring the connecting structure thereof, andthe optically reconfiguring input/output circuit is arranged at least three vertexes of a quadrangular logical circuit chip on which the logical circuit is mounted.
[claim9]
9. The optically reconfigurable gate array according to claim 8, wherein the output state detection circuit comprises: a voltage detection circuit that detects a voltage of the output terminal of a logical signal of the logical circuit;
and
a detection voltage applying circuit that applies a voltage not less than a logical threshold or voltage not more than the logical value to the output terminal of the logical signal of the logical circuit via a resistor.
[claim10]
10. The write state inspection device according to claim 5, wherein the logical circuit for inspection has a logical structure in which the output of the output terminal of the logical circuit chip changes depending on the input of the optical signal to the optically reconfigurable bit element as an inspection target.
[claim11]
11. The write state inspection device according to claim 5, wherein the output-state detection means comprises: a voltage detection circuit that detects a voltage of the output terminal of the logical circuit;
and
a detection voltage applying circuit that switchably applies a voltage not less than a logical threshold or voltage not more than the logical threshold to the output terminal of the logical circuit via a resistor.
[claim12]
12. The write state inspection device according to claim 6, wherein the output-state detection means comprises: a voltage detection circuit that detects a voltage of the output terminal of the logical circuit;
and
a detection voltage applying circuit that switchably applies a voltage not less than a logical threshold or voltage not more than the logical threshold to the output terminal of the logical circuit via a resistor.
[claim13]
13. The write state inspection device according to claim 10, wherein the output-state detection means comprises: a voltage detection circuit that detects a voltage of the output terminal of the logical circuit;
and
a detection voltage applying circuit that switchably applies a voltage not less than a logical threshold or voltage not more than the logical threshold to the output terminal of the logical circuit via a resistor.
  • 発明者/出願人(英語)
  • WATANABE MINORU
  • KOBAYASHI FUMINORI
  • JAPAN SCIENCE AND TECHNOLOGY AGENCY
  • KYUSHU UNIVERSITY INSTITUTE OF TECHNOLOGY
国際特許分類(IPC)
米国特許分類/主・副
  • G01R031/317W
  • G01R031/3185P
  • H03K019/177H
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