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Context switching system having context cache and a register file for the save and restore context operation

外国特許コード F120006786
整理番号 B11-01WO
掲載日 2012年6月26日
出願国 アメリカ合衆国
出願番号 54118703
公報番号 20070022428
公報番号 8020169
出願日 平成15年12月11日(2003.12.11)
公報発行日 平成19年1月25日(2007.1.25)
公報発行日 平成23年9月13日(2011.9.13)
国際出願番号 JP2003015838
国際公開番号 WO2004063925
国際出願日 平成15年12月11日(2003.12.11)
国際公開日 平成16年7月29日(2004.7.29)
優先権データ
  • 特願2003-003038 (2003.1.9) JP
  • 2003WO-JP15838 (2003.12.11) WO
発明の名称 (英語) Context switching system having context cache and a register file for the save and restore context operation
発明の概要(英語) (US8020169)
In an application in which context switching often occurs such as in a real time OS, it is possible to significantly reduce the overhead caused by the context switching.
The OS issues a Swap instruction and a context switch starts.
The Swap instruction is issued together with a thread (i.e., context) ID to be replaced, to a thread control unit (9).
The thread ID is used to uniquely identify threads stored in a context cache (8).
The thread control unit (9) saves data from a register file (1) to the context cache (8) via a context-dedicated bus (12) and transmits data of a new thread from the context cache (8) to the register file (1).
According to the thread ID received, the thread control unit (9) automatically interchanges the necessary number of data in the register file (1) and the data in the context cache (8).
特許請求の範囲(英語) [claim1]
1. A context switching unit for switching a plurality of contexts, the context switching unit comprising: a register file having stored a context related to a thread to be executed by an arithmetic logic unit or a memory access unit, the register file comprising a register read port, a register write port, a context-switching read port, and a context-switching write port;
a context cache used exclusively for saving and restoring contexts, the context cache comprising a read port and a write port, being connected directly to the register file and integrated in a central processing unit on a chip, the context cache being not connected to a memory through a bus, which connects the memory, an instruction cache and a data cache to each other, and being independent from a memory system including the memory, the instruction cache and the data cache, to realize context switching at a high processing speed without interference from the bus;
a context switching bus for connecting the register file and the context cache, the context switching bus comprising a restore bus and a save bus for connecting the read port and the write port of the context cache to the context-switching write port and the context-switching read port of the register file respectively; and
a thread control unit for controlling data transfer between the context cache and the register file, the thread control unit comprising a thread identifier table for storing a thread identifier for identifying the context of a thread stored in the context cache and being connected in parallel with the arithmetic logic unit and the memory access unit,
wherein, in case of a context switch operation which executes both a save operation for saving a context from the register file to the context cache and a restore operation for restoring a context from the context cache to the register file in parallel at the same time, the thread control unit receives a context switch instruction for executing the context switch operation with the identifier of a new thread to be interchanged;
the thread control unit obtains a restore address where a new context to be interchanged is stored in the context cache and a save register identifier indicating a location where a current context is stored in the register file, by searching through the thread identifier table in accordance with the thread identifier;
the thread control unit sends the obtained address to the context cache and the register identifier to the register file;
in parallel at the same time;
the register file, in accordance with the register identifier given by the thread control unit, outputs the data of the context to be saved from the context-switching read port to the save bus for the save operation and holds the data of the context to be in parallel at the same time, sent from the read port of the context cache to the context-switching write port through the restore for the restore operation;
the context cache, in accordance with the address given by the thread control unit, outputs the data of a context to be restored from the read port to the restore bus for the restore operation and holds the data of the context to be saved in parallel at the same time, sent from the context-switching read port of the register file to the write port via the save bus for the save operation; and
whereby the context switching unit switches contexts the context switch operation which executes both the restore operation and the save operation in parallel at the same time.
[claim2]
2. The context switching unit according to claim 1, wherein the context switching bus has a bus width greater than a bit width of the register file.
[claim3]
3. The context switching unit according to claim 1, wherein the thread control unit comprises as many thread identifier tables as required to identify contexts cached in the context cache.
[claim4]
4. The context switching unit according to claim 1, wherein the thread control unit saves the context of the current thread from the register file to the context cache and sends the context of a new thread from the context cache to the register file in parallel at the same time to automatically interchange a required number of data items between the register file and the context cache, when software, such as an operating system, issues a swap instruction for interchanging contexts, including a thread identifier as an operand, if the swap instruction is executed.
[claim5]
5. The context switching unit according to claim 1, wherein the thread control unit transfers the data of a context from the register file to the context cache and does not transfer the data of a context from the context cache to the register file, when software, such as an operating system, issues a backup instruction for saving a context, including a thread identifier as an operand, if the backup instruction is executed.
[claim6]
6. The context switching unit according to claim 1, wherein the thread control unit transfers the data of a context from the context cache to the register file and does not transfer the data of a context from the register file to the context cache, when software, such as an operating system, issues a restore instruction for restoring a context, including a thread identifier as an operand, if the restore instruction is executed.
[claim7]
7. A central processing unit comprising: a context switching unit according claim 1;
the instruction cache for caching an instruction and the data cache for caching data;
an instruction fetch unit for fetching the instruction from the instruction cache and decoding the instruction;
the memory access unit for accessing the data cache and memory, and executing a load or store operation; and
an arithmetic bus for connecting the register file, the arithmetic logic unit, the memory access unit, and the thread control unit in parallel.
[claim8]
8. The central processing unit according to claim 7, wherein the memory access unit sends an address and data to the data cache and stores the data in the data cache when a store instruction is given, and the memory access unit sends an address to the data cache, reads data from the data cache, and writes the read data back into the register file when a load instruction is given.
[claim9]
9. A context switching method for switching a plurality of contexts by using a context switching unit comprising: storing a context related to a thread in a register file to be executed by an arithmetic logic unit or a memory access unit, the register file comprising a register read port, a register write port, a context-switching read port, and a context-switching write port;
saving and restoring contexts exclusively in a context cache, the context cache comprising a read port and a write port, being connected directly to the register file and integrated in a central processing unit; on a chip, the context cache being not connected to a memory through a bus, which connects the memory, an instruction cache and a data cache to each other, and being independent from a memory system including the memory, the instruction cache and the data cache, to realize context switching at a high processing speed without interference from the bus;
connecting the register file and the context cache with a context switching bus, the context switching bus comprising a restore bus and a save bus for connecting the read port and the write port of the context cache to the context-switching write port and the context-switching read port of the register file respectively; and
controlling data transfer between the context cache and the register file using a thread control unit, the thread control unit comprising a thread identifier table for storing a thread identifier for identifying the context of a thread stored in the context cache and being connected in parallel with the arithmetic logic unit and the memory access unit,
wherein, in case of a context switch operation which executes both a save operation for saving a context from the register file to the context cache and a restore operation for restoring a context from the context cache to the register file in parallel at the same time, the thread control unit receives a context switch instruction for executing the context switch operation with the identifier of a new thread to be interchanged;
the thread control unit obtains a restore address where a new context to be interchanged is stored in the context cache and a save register identifier indicating a location where a current context is stored in the register file, by searching through the thread identifier table in accordance with the thread identifier;
the thread control unit sends the obtained address to the context cache and the register identifier to the register file in parallel at the same time;
the register file, in accordance with the register identifier given by the thread control unit, outputs the data of the context to be saved from the context-switching read port to the save bus for the save operation and holds the data of the context to be restored in parallel at the same time, sent from the read port of the context cache to the context-switching write port through the restore bus for the restore operation;
the context cache, in accordance with the address given by the thread control unit, outputs the data of the context to be restored from the read port to the restore bus for the restore operation and holds the data of the context to be saved in parallel at the same time, sent from the context-switching read port of the register file to the write port via the save bus; for the save operation; and
whereby the context switching unit switches contexts by the context switch operation which executes both the restore operation and the save operation in parallel at the same time.
[claim10]
10. The context switching method according to claim 9, saving the context of the current thread from the register file to the context cache and sending the context of a new thread from the context cache to the register file concurrently to automatically interchange a required number of data items between the register file and the context cache, when software, such as an operating system, issuing a swap instruction for interchanging contexts, including a thread identifier as an operand, if the swap instruction is executed.
[claim11]
11. The context switching method according to claim 9, transferring the data of a context from the register file to the context cache and not transferring the data of a context from the context cache to the register file, when software, such as an operating system, issuing a backup instruction for saving a context, including a thread identifier as an operand, if the backup instruction is executed.
[claim12]
12. The context switching method according to claim 9, transferring the data of a context from the context cache to the register file and not transferring the data of a context from the register file to the context cache, when software, such as an operating system, issuing a restore instruction for restoring a context, including a thread identifier as an operand, if the restore instruction is executed.
[claim13]
13. A computer comprising a context switching program for switching a plurality of contexts by using a context switching unit the context switching unit comprising: a register file having stored a context related to a thread to be executed by an arithmetic logic unit or a memory access unit, the register file comprising a register read port, a register write port, a context-switching read port, and a context-switching write port;
a context cache used exclusively for saving and restoring contexts, the context cache comprising a read port and a write port, connected directly to the register file and integrated in a central processing unit on a chip, the context cache being not connected to a memory through a bus, which connects the memory, an instruction cache and a data cache to each other, and being independent from a memory system including the memory, the instruction cache and the data cache, to realize context switching at a high processing speed without interference from the bus;
a context switching bus for connecting the register file and the context cache, the context switching bus comprising a restore bus and a save bus for connecting the read port and the write port of the context cache to the context-switching write port and the context-switching read port of the register file respectively; and
a thread control unit for controlling data transfer between the context cache and the register file, the thread control unit comprising a thread identifier table for storing a thread identifier for identifying the context of a thread stored in the context cache and being connected in parallel with the arithmetic logic unit and the memory access unit,
the context switching program causing the computer to execute:
a step wherein, in case of a context switch operation which executes both a save operation for saving a context from the register file to the context cache and a restore operation for restoring a context from the context cache to the register file in parallel at the same time, the thread control unit receives a context switch instruction for executing the context switch operation with the identifier of a new thread to be executes both a context save operation and a context restore operation in interchanged;
a step in which the thread control unit obtains a restore address where a new context to be interchanged is stored in the context cache and the save register identifier indicating the location where the current context is stored in the register file, by searching through the thread identifier table in accordance with the thread identifier;
a step in which the thread control unit sends the obtained address to the context cache and the register identifier to the register file in parallel at the same time;
a step in which the register file, in accordance with the register identifier given by the thread control unit, outputs the data of the context to be saved from the context-switching read port to the save bus for the save operation and holds the data of the context to be restored in parallel at the same time, sent from the read port of the context cache to the context-switching write port through the restore bus for the restore operation in the register corresponding to the register identifier;
a step in which the context cache, in accordance with the address given by the thread control unit, outputs the data of the context to be restored from the read port to the restore bus for the restore operation and holds the data of the context to be saved in parallel at the same time, sent from the context-switching read port of the register file to the write port via the save bus for the save operation; and
whereby the context switching unit switches contexts by the context switch operation which executes both the restore operation and the save operation in parallel at the same time.
  • 発明者/出願人(英語)
  • YAMASAKI NOBUYUKI
  • JAPAN SCIENCE AND TECHNOLOGY AGENCY
国際特許分類(IPC)
参考情報 (研究プロジェクト等) SORST Selected in Fiscal 2000
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