Top > Search of International Patents > ASYNCHRONOUS MEMORY ELEMENT FOR SCANNING, SEMICONDUCTOR INTEGRATED CIRCUIT PROVIDED WITH SAME, DESIGN METHOD THEREOF, AND TEST PATTERN GENERATION METHOD

ASYNCHRONOUS MEMORY ELEMENT FOR SCANNING, SEMICONDUCTOR INTEGRATED CIRCUIT PROVIDED WITH SAME, DESIGN METHOD THEREOF, AND TEST PATTERN GENERATION METHOD

Foreign code F120006867
File No. S2010-0874-C0
Posted date Sep 20, 2012
Country WIPO
International application number 2011JP003405
International publication number WO 2011/158500
Date of international filing Jun 15, 2011
Date of international publication Dec 22, 2011
Priority data
  • P2010-138609 (Jun 17, 2010) JP
Title ASYNCHRONOUS MEMORY ELEMENT FOR SCANNING, SEMICONDUCTOR INTEGRATED CIRCUIT PROVIDED WITH SAME, DESIGN METHOD THEREOF, AND TEST PATTERN GENERATION METHOD
Abstract

The disclosed asynchronous memory element for scanning is provided with an n-input asynchronous memory element (12), and a scan control logic circuit (14) that generates the n-input for the asynchronous memory element (12) from an n-bit signal input and scan input. The scan control logic circuit (14) outputs, as the n-input for each asynchronous memory element (12), a signal input when the control signal applied is a first bit pattern, a scan input when the signal is a second bit pattern, and a bit pattern where the asynchronous memory element (12) retains a previous value at all other times.

  • Applicant
  • ※All designated countries except for US in the data before July 2012
  • NATIONAL UNIVERSITY CORPORATION NARA INSTITUTE OFSCIENCE AND TECHNOLOGY,
  • OHTAKE, SATOSHI,
  • IWATA, HIROSHI,
  • INOUE, MICHIKO
  • Inventor
  • OHTAKE, SATOSHI,
  • IWATA, HIROSHI,
  • INOUE, MICHIKO
IPC(International Patent Classification)
Please contact us by E-mail or facsimile if you have any interests on this patent.

PAGE TOP

close
close
close
close
close
close