ASYNCHRONOUS DATA TRANSFER DEVICE
Provided is an asynchronous data transfer device able to detect a wiring fault without a delay assumption by monitoring the amount of current, and having both delay fault tolerance and wiring fault tolerance at the same time. An LSI asynchronous data transfer device (1) installed between IP cores comprises a first wiring (3a) connected to a first IP core, a second wiring (3b) connected to a second IP core, a transmitter (2) connected to the first wiring (3a), a receiver (4) connected to the second wiring (3b), and a third wiring (3c) connecting the transmitter (2) and the receiver (4). The transmitter (2) comprises: an input unit (2A) having an encoder (5) and an input controller (6)
and an output unit (2B). The encoder (5) of the transmitter (2) is provided with current driver circuits (11a, 11b, 11c, 11d) for detecting an open fault of the third wiring (3c).