Memory cell block, manufacturing method therefor, memory device, and method for driving a memory device
This memory cell block is provided with a plurality of memory cells connected in series, each memory cell comprising a solid-state electronic element in which the following are connected in parallel: an information-storage transistor (TR1) that has a first gate-insulating layer comprising a ferroelectric layer
and an information-reading/writing transistor (TR2) that has a second gate-insulating layer. First channel regions and second channel regions comprise conductor layers or semiconductor layers formed in the same step. Each two adjacent memory cells are connected by a connection layer contiguous with the first channel regions and the second channel regions. When this memory cell block is used as a NAND memory device, the "write disturb problem" and "read disturb problem" are eliminated. Also, it is possible to form the first channel regions, the second channel regions, and the connection layers in one step. Furthermore, it is possible to reduce the contact resistance between the first and second channel regions and the connection layers.