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CLOCK DATA RECOVERY CIRCUIT AND WIRELESS MODULE INCLUDING SAME

Foreign code F130007205
File No. S2012-1009-N0
Posted date Mar 7, 2013
Country WIPO
International application number 2011JP053416
International publication number WO 2012/111133
Date of international filing Feb 17, 2011
Date of international publication Aug 23, 2012
Title CLOCK DATA RECOVERY CIRCUIT AND WIRELESS MODULE INCLUDING SAME
Abstract

This clock data recovery circuit (11) is provided with: a ring oscillator (17)

an oscillation control circuit unit (15) which starts and stops operation of the ring oscillator (17) depending upon the presence or absence of input of a PWM signal

a counter circuit unit (19) for counting pulse signals and holding an N-bit count value

a register circuit unit (21) which has an M-bit register and is configured so as to be able to transfer the upper M bits among the N-bit count value as a reference count value in response to the input of a transfer signal

a comparator circuit unit (25) which outputs a timing clock if the count number held by the counter circuit unit (19) exceeds the reference count value held by the register circuit unit (21)

and a transfer control circuit unit (23) which, in synchronization with the start-up timing of the PWM signal, generates the transfer signal for transferring the reference count value from the counter circuit unit (19) to the register circuit unit (21) and a reset signal for resetting the counter circuit unit (19).

  • Applicant
  • ※All designated countries except for US in the data before July 2012
  • NATIONAL UNIVERSITY CORPORATION HOKKAIDO UNIVERSITY,
  • SANO EIICHI,
  • AMEMIYA YOSHIHITO
  • Inventor
  • SANO EIICHI,
  • AMEMIYA YOSHIHITO
IPC(International Patent Classification)
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