LAMINATED STRUCTURE, FERROELECTRIC GATE THIN FILM TRANSISTOR, AND FERROELECTRIC THIN FILM CAPACITOR
This ferroelectric gate thin film transistor (20) comprises: a channel layer (28)
a gate electrode layer (22) that controls the conduction state of the channel layer (28)
and a gate insulation layer (25) comprising a ferroelectric layer arranged between the channel layer (28) and the gate electrode layer (22). The gate insulation layer (ferroelectric layer) (25) has a structure wherein a PZT layer (23) and a BLT layer (24) (Pb diffusion-preventing layer) are stacked
and the channel layer (28) (oxide conductor layer) (28) is arranged on a surface on the BLT layer (Pb diffusion-preventing layer) (24) side of the gate insulation layer (ferroelectric layer) (25). This ferroelectric gate thin film transistor (20) is capable of solving a variety of issues, such as the issue of ready deterioration of transmission properties of ferroelectric gate thin film transistors (e.g., ready narrowing of memory window width), and other issues that may arise caused by diffusion of Pb atoms from PZT layers in oxide conductor layers.