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LAMINATED STRUCTURE, FERROELECTRIC GATE THIN FILM TRANSISTOR, AND FERROELECTRIC THIN FILM CAPACITOR

Foreign code	F130007388
File No.	E086P33
Posted date	Jun 5, 2013
Country	WIPO
International application number	2012JP077326
International publication number	WO 2013/073347
Date of international filing	Oct 23, 2012
Date of international publication	May 23, 2013
Priority data	P2011-252182 (Nov 18, 2011) JP
Title	LAMINATED STRUCTURE, FERROELECTRIC GATE THIN FILM TRANSISTOR, AND FERROELECTRIC THIN FILM CAPACITOR
Abstract	This ferroelectric gate thin film transistor (20) comprises: a channel layer (28) a gate electrode layer (22) that controls the conduction state of the channel layer (28) and a gate insulation layer (25) comprising a ferroelectric layer arranged between the channel layer (28) and the gate electrode layer (22). The gate insulation layer (ferroelectric layer) (25) has a structure wherein a PZT layer (23) and a BLT layer (24) (Pb diffusion-preventing layer) are stacked and the channel layer (28) (oxide conductor layer) (28) is arranged on a surface on the BLT layer (Pb diffusion-preventing layer) (24) side of the gate insulation layer (ferroelectric layer) (25). This ferroelectric gate thin film transistor (20) is capable of solving a variety of issues, such as the issue of ready deterioration of transmission properties of ferroelectric gate thin film transistors (e.g., ready narrowing of memory window width), and other issues that may arise caused by diffusion of Pb atoms from PZT layers in oxide conductor layers.
Applicant ※All designated countries except for US in the data before July 2012	JAPAN SCIENCE AND TECHNOLOGY AGENCY
Inventor	SHIMODA, TATSUYA, MIYASAKO, TAKAAKI, TOKUMITSU, EISUKE, BUI NGUYEN QUOC TRINH
IPC(International Patent Classification)	H01L 21/8246 Read-only memory structures (ROM) C01G 29/00 Compounds of bismuth C01G 35/00 Compounds of tantalum H01L 21/28 Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups ; H01L0021200000-H01L0021268000 H01L 21/283 Deposition of conductive or insulating materials for electrodes H01L 21/316 composed of oxides or glassy oxides or oxide-based glass H01L 21/336 with an insulated gate H01L 21/368 using liquid deposition H01L 21/822 the substrate being a semiconductor, using silicon technology;; H01L 27/04 the substrate being a semiconductor body H01L 27/105 including field-effect components H01L 29/423 not carrying the current to be rectified, amplified or switched H01L 29/49 Metal-insulator semiconductor electrodes H01L 29/786 Thin-film transistors H01L 29/788 with floating gate H01L 29/792 with charge trapping gate insulator, e.g. MNOS-memory transistor H01L 41/09 with electrical input and mechanical output H01L 41/18 for piezo-electric or electrostrictive elements H01L 41/22 Processes or apparatus specially adapted for the assembly, manufacture or treatment of piezo-electric or electrostrictive devices or of parts thereof H01L 41/39 Inorganic materials
Reference ( R and D project )	ERATO SHIMODA Nano-Liquid Process AREA

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Contact Information for " LAMINATED STRUCTURE, FERROELECTRIC GATE THIN FILM TRANSISTOR, AND FERROELECTRIC THIN FILM CAPACITOR "

Japan Science and Technology Agency Department of Intellectual Property Management
URL: http://www.jst.go.jp/chizai/
E-mail:
Address: 5-3, Yonbancho, Chiyoda-ku, Tokyo, Japan , 102-8666
Fax: 81-3-5214-8476

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Contact Information for " LAMINATED STRUCTURE, FERROELECTRIC GATE THIN FILM TRANSISTOR, AND FERROELECTRIC THIN FILM CAPACITOR "

Japan Science and Technology Agency Department of Intellectual Property Management
URL: http://www.jst.go.jp/chizai/
E-mail:
Address: 5-3, Yonbancho, Chiyoda-ku, Tokyo, Japan , 102-8666
Fax: 81-3-5214-8476

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Gazette	WO 2013/073347(PDF,3576KB)