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TEST PATTERN MANUFACTURING DEVICE, FAULT DETECTION SYSTEM, TEST PATTERN MANUFACTURING METHOD, PROGRAM, AND RECORDING MEDIUM meetings

Foreign code F130007589
File No. S2012-0301-N0
Posted date Jul 31, 2013
Country WIPO
International application number 2013JP050150
International publication number WO 2013/105564
Date of international filing Jan 9, 2013
Date of international publication Jul 18, 2013
Priority data
  • P2012-002214 (Jan 10, 2012) JP
Title TEST PATTERN MANUFACTURING DEVICE, FAULT DETECTION SYSTEM, TEST PATTERN MANUFACTURING METHOD, PROGRAM, AND RECORDING MEDIUM meetings
Abstract

Provided are a test pattern manufacturing device, etc., with which, while effecting characteristic maintenance of an original test pattern, it is possible to manufacture a new test pattern. This test pattern manufacturing device, which manufactures a test pattern which is inputted into a test object circuit of a scan test, comprises logic value generation means for generating a new logic value by referring to the logic values of a supplied first bit, second bit, and third bit, and either maintaining or inverting the logic value of the second bit. The logic value of the first bit is either that which an initial test pattern which is a supplied test pattern has, or that which a new test pattern which the test pattern manufacturing device has manufactured on the basis of the initial test pattern has. The logic value of the second bit is that which the initial test pattern has. The logic value of the third bit is either that which the initial test pattern has, or that which the new test pattern has.

  • Applicant
  • ※All designated countries except for US in the data before July 2012
  • KYUSHU INSTITUTE OF TECHNOLOGY
  • Inventor
  • SATO YASUO,
  • KAJIHARA SEIJI
IPC(International Patent Classification)
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