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FAILURE DETECTION SYSTEM, GENERATING CIRCUIT AND PROGRAM

外国特許コード	F130007788
整理番号	S2012-0746-N0
掲載日	2013年12月16日
出願国	世界知的所有権機関（ＷＩＰＯ）
国際出願番号	2013JP063393
国際公開番号	WO 2013/175998
国際出願日	平成25年5月14日(2013.5.14)
国際公開日	平成25年11月28日(2013.11.28)
優先権データ	特願2012-117842 (2012.5.23) JP
発明の名称（英語）	FAILURE DETECTION SYSTEM, GENERATING CIRCUIT AND PROGRAM
発明の概要（英語）	The purpose of the invention is to provide items such as a failure detection system capable of providing for a reduction in shift power at the time of a scan-out, while maintaining a failure detection rate. The invention is the failure detection system, which by means of a scan test, detects a failure in a logic circuit, said failure detection system being provided with: multiple flip-flops a final signal generating means that generates a final signal that indicates that a final capture in a capture mode is said final capture a specification means that is different from both the logic circuit and the flip-flops, and that for a portion of the flip-flops, specifies a logic value if the final signal is received and a failure detection device that performs a failure detection by making a comparison. Said comparison is between: test output captured from the logic circuit, said test output containing a logic value specified by the specification means and test output when the logic circuit has not failed, said test output containing a logic value specified by the specification means.
出願人（英語） ※2012年7月以前掲載分については米国以外のすべての指定国	KYUSHU INSTITUTE OF TECHNOLOGY
発明者（英語）	SATO YASUO, WANG SENLING, MIYASE KOHEI, KAJIHARA SEIJI
国際特許分類(IPC)	G01R 31/28 電子回路の試験，例．シグナルトレーサーによるもの H01L 21/822 基板がシリコン技術を用いる半導体であるもの H01L 27/04 基板が半導体本体であるもの