FAILURE DETECTION SYSTEM, GENERATING CIRCUIT AND PROGRAM
外国特許コード | F130007788 |
---|---|
整理番号 | S2012-0746-N0 |
掲載日 | 2013年12月16日 |
出願国 | 世界知的所有権機関(WIPO) |
国際出願番号 | 2013JP063393 |
国際公開番号 | WO 2013/175998 |
国際出願日 | 平成25年5月14日(2013.5.14) |
国際公開日 | 平成25年11月28日(2013.11.28) |
優先権データ |
|
発明の名称 (英語) |
FAILURE DETECTION SYSTEM, GENERATING CIRCUIT AND PROGRAM
|
発明の概要(英語) |
The purpose of the invention is to provide items such as a failure detection system capable of providing for a reduction in shift power at the time of a scan-out, while maintaining a failure detection rate. The invention is the failure detection system, which by means of a scan test, detects a failure in a logic circuit, said failure detection system being provided with: multiple flip-flops a final signal generating means that generates a final signal that indicates that a final capture in a capture mode is said final capture a specification means that is different from both the logic circuit and the flip-flops, and that for a portion of the flip-flops, specifies a logic value if the final signal is received and a failure detection device that performs a failure detection by making a comparison. Said comparison is between: test output captured from the logic circuit, said test output containing a logic value specified by the specification means and test output when the logic circuit has not failed, said test output containing a logic value specified by the specification means. |
|
|
|
|
国際特許分類(IPC) |
|
日本語項目の表示
発明の名称 |
故障検出システム、生成回路及びプログラム
|
---|
『 FAILURE DETECTION SYSTEM, GENERATING CIRCUIT AND PROGRAM 』に関するお問合せ
- 国立大学法人九州工業大学 オープンイノベーション推進機構 産学官連携本部
- URL: http://www.ccr.kyutech.ac.jp/
-
E-mail:
- Address: 〒804-8550 福岡県北九州市戸畑区仙水町1-1
- TEL: 093-884-3499
- FAX: 093-884-3531