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Method for manufacturing silicon-carbide semiconductor element

Foreign code F160008778
File No. KG0119-US01
Posted date Aug 3, 2016
Country United States of America
Application number 201414897380
Gazette No. 20160111279
Gazette No. 9941116
Date of filing Jun 6, 2014
Gazette Date Apr 21, 2016
Gazette Date Apr 10, 2018
International application number JP2014003048
International publication number WO2014199614
Date of international filing Jun 6, 2014
Date of international publication Dec 18, 2014
Priority data
  • P2013-125018 (Jun 13, 2013) JP
  • 2014WO-JP03048 (Jun 6, 2014) WO
Title Method for manufacturing silicon-carbide semiconductor element
Abstract (US9941116)
In this method for manufacturing a semiconductor element, a modified layer produced by subjecting a substrate (70) to mechanical polishing is removed by heating the substrate (70) under Si vapor pressure.
An epitaxial layer formation step, an ion implantation step, an ion activation step, and a second removal step are then performed.
In the second removal step, macro-step bunching and insufficient ion-implanted portions of the surface of the substrate (70) performed the ion activation step are removed by heating the substrate (70) under Si vapor pressure.
After that, an electrode formation step in which electrodes are formed on the substrate (70) is performed.
Scope of claims [claim1]
1. A method for manufacturing a semiconductor element using a substrate having an off angle, the substrate having at least its surface made of a SiC layer, the substrate having been cut from an ingot, the method comprising: a mechanical polishing step which forms polishing scratches and a modified layer within the polishing scratches on the substrate;
a first removal step of removing the polishing scratches and the modified layer within the polishing scratches of about 10 mu m produced by subjecting the substrate to the mechanical polishing step, by heating the substrate under Si vapor pressure and performing isotropic etching based upon etching rate to reciprocal of heating temperature;
an epitaxial layer formation step of forming an epitaxial layer on the substrate that is the modified layer is removed;
an ion implantation step of implanting ions on the epitaxial layer;
an ion activation step of activating ions by heating the substrate;
a second removal step of removing at least one insufficient ion-implanted portion of the surface of the substrate that is the ion activation step is performed thereon and a macro-step bunching occurred on the surface of the substrate during the ion activation step by heating the substrate under Si vapor pressure; and
an electrode formation step of forming at least one electrode on the substrate from which the at least one insufficient ion-implanted portion and macro-step bunching are removed by the second removal step.
[claim2]
2. The method for manufacturing the semiconductor element according to claim 1, wherein in the first removal step, heating is performed in a temperature range of 1800 deg. C. or more and 2300 deg. C. or less and under Si vapor pressure of 10-2 Pa or more.
[claim3]
3. The method for manufacturing the semiconductor element according to claim 1, wherein in the epitaxial layer formation step, an epitaxial layer is formed using a chemical vapor deposition method.
[claim4]
4. The method for manufacturing the semiconductor element according to claim 1, wherein in the epitaxial layer formation step, an epitaxial layer is formed using a liquid-phase epitaxial method.
[claim5]
5. The method for manufacturing the semiconductor element according to claim 1, wherein in the ion activation step, heating is performed in a temperature range of 1800 deg. C. or more and 2300 deg. C. or less and under Si vapor pressure of 10-3 Pa or less.
[claim6]
6. The method for manufacturing the semiconductor element according to claim 1, wherein in the second removal step, heating is performed in a temperature range of 1600 deg. C. or more and 2000 deg. C. or less and under Si vapor pressure of 10-3 Pa or less.
[claim7]
7. The method for manufacturing the semiconductor element according to claim 1, wherein the surface of the SiC layer has an off angle of 4 degrees or less in the direction of <11-20>.
[claim8]
8. The method for manufacturing the semiconductor element according to claim 1, wherein the surface of the SiC layer has an off angle of 4 degrees or less in the direction of <1-100>.
[claim9]
9. The method for manufacturing the semiconductor element according to claim 1, wherein the surface of the SiC layer terminates at a step having a full-unit height that corresponds to one periodic of SiC molecules in a stack direction or a half-unit height that corresponds to one-half periodic thereof.
[claim10]
10. The method for manufacturing the semiconductor element according to claim 1, wherein the electrode formation step and the second removal step are continuously performed using a common heating apparatus.
[claim11]
11. The method for manufacturing the semiconductor element according to claim 1, wherein in consideration of the relationship between heating condition including Si vapor pressure, heating temperature, and etching rate and the presence or absence of occurrence of the macro-step bunching, the heating condition is determined in at least either one of the first removal step or the second removal step.
[claim12]
12. The method for manufacturing the semiconductor element according to claim 1, wherein the first removal step is performed at the etching rate of about 100 nm/min or more.
  • Inventor, and Inventor/Applicant
  • KANEKO TADAAKI
  • OHTANI NOBORU
  • HAGIWARA KENTA
  • KWANSEI GAKUIN
IPC(International Patent Classification)
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