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SEMICONDUCTOR INTEGRATED CIRCUIT AND DELAY MEASUREMENT CIRCUIT

Foreign code F160008877
File No. (S2015-0412-N0)
Posted date Oct 25, 2016
Country WIPO
International application number 2016JP001185
International publication number WO 2016139958
Date of international filing Mar 4, 2016
Date of international publication Sep 9, 2016
Priority data
  • P2015-044113 (Mar 5, 2015) JP
Title SEMICONDUCTOR INTEGRATED CIRCUIT AND DELAY MEASUREMENT CIRCUIT
Abstract A semiconductor integrated circuit according to one aspect of the present invention is provided with: a circuit unit to be measured provided with a plurality of connected flip-flop circuits; a clock generation circuit unit; and a delay measurement circuit unit which is provided with a NAND circuit, a plurality of NOT circuits connected in series with the NAND circuit, a counter circuit connected to terminals of the plurality of NOT circuits, and a scan chain circuit in which a plurality of selector circuits and a plurality of flip-flop circuits are connected. The NAND circuit is provided with at least two bias voltage input gates.
Outline of related art and contending technology BACKGROUND ART
The semiconductor integrated circuit, semiconductor material or insulating surface of the material or a semiconductor material with transistors of other circuit elements are generated, the function of the electronic circuit and is designed to have, a personal computer or a mobile phone or the like is used and, particularly in recent years, advances in miniaturization in the semiconductor integrated circuit technology and high-speed been prominently.
However, the high speed operation of the semiconductor integrated circuit, variations in machining the variation in the increase in capacitive coupling between the lines due to the variation of the propagation time of signals in the circuit results, how important is to reduce this variation has been a problem. That is a high-speed semiconductor integrated circuit in the circuit in order to manufacture a better yield the propagation time and determine the statistical variation, it is possible that improvement is necessary. The propagation time is longer than necessary as the method of confirming whether or not the delay measurement that.
Delay measurement is, a test signal is input and the response signal to be measured is referred to as a time to obtain, as a result, the measured time falls within a predetermined period of time to determine whether or not, whether or not a defective product can be determined.
However, the delay built in the semiconductor integrated circuit itself is also measured under the influence of a manufacturing variation, and due to the variation of the measurement itself. In this case, it is difficult to perform accurate delay measurement becomes.
Therefore, used in the known techniques, for example in the following Patent Document 1 and 2, delay measurement circuit to reduce the measurement error due to a variation in the disclosed technique.
Scope of claims (In Japanese)[請求項1]
クロック生成回路と、
論理出力回路と、前記論理出力回路に直列に接続される複数の遅延回路と、前記複数の遅延回路の末端に接続されるカウンタ回路と、を有する遅延測定回路と、を備えた遅延測定回路であって、
前記論理出力回路及び前記複数の遅延回路の少なくとも一つは、遅延時間可変である遅延測定回路。
[請求項2]
前記論理出力回路は、NAND回路及びNOR回路の少なくともいずれかを含む請求項1記載の遅延測定回路。
[請求項3]
前記遅延回路は、NOT回路及びバッファ回路の少なくともいずれかを含む請求項1記載の遅延測定回路。
[請求項4]
複数のセレクタ回路及び複数のフリップフロップ回路が接続されたスキャンチェーン回路を備える請求項1記載の遅延測定回路。
[請求項5]
被測定回路と、
クロック生成回路と、
論理出力回路と、前記論理出力回路に直列に接続される複数の遅延回路と、前記複数の遅延回路の末端に接続されるカウンタ回路と、を有する遅延測定回路と、を備えた半導体集積回路であって、
前記論理出力回路及び前記複数の遅延回路の少なくとも一つは、少なくとも二つのバイアス電圧入力ゲートを備える半導体集積回路。
[請求項6]
前記論理出力回路は、NAND回路及びNOR回路の少なくともいずれかを含む請求項5記載の半導体集積回路。
[請求項7]
前記遅延回路は、NOT回路及びバッファ回路の少なくともいずれかを含む請求項5記載の半導体集積回路。
[請求項8]
複数のセレクタ回路及び複数のフリップフロップ回路が接続されたスキャンチェーン回路を備える請求項5記載の半導体集積回路。
[請求項9]
接続された複数のフリップフロップ回路を有する被測定回路と、
クロック生成回路と、
NAND回路と、前記NAND回路に直列に接続される複数のNOT回路と、複数の前記NOT回路の末端に接続されるカウンタ回路と、複数のセレクタ回路及び複数のフリップフロップ回路が接続されるスキャンチェーン回路と、を有する遅延測定回路と、を備えた半導体集積回路であって、
前記NAND回路は、少なくとも二つのバイアス電圧入力ゲートを備える半導体集積回路。
[請求項10]
NAND回路と、前記NAND回路に直列に接続される複数のNOT回路と、複数の前記NOT回路の末端に接続されるカウンタ回路と、複数のセレクタ回路及び複数のフリップフロップ回路が接続されるスキャンチェーン回路と、を備え、
前記NAND回路は、少なくとも二つのバイアス電圧入力ゲートを備えた遅延測定回路。
  • Applicant
  • ※All designated countries except for US in the data before July 2012
  • NATIONAL UNIVERSITY CORPORATION CHIBA UNIVERSITY
  • Inventor
  • NAMBA, Kazuteru
  • CUI, Ri
IPC(International Patent Classification)
Specified countries National States: AE AG AL AM AO AT AU AZ BA BB BG BH BN BR BW BY BZ CA CH CL CN CO CR CU CZ DE DK DM DO DZ EC EE EG ES FI GB GD GE GH GM GT HN HR HU ID IL IN IR IS JP KE KG KN KP KR KZ LA LC LK LR LS LU LY MA MD ME MG MK MN MW MX MY MZ NA NG NI NO NZ OM PA PE PG PH PL PT QA RO RS RU RW SA SC SD SE SG SK SL SM ST SV SY TH TJ TM TN TR TT TZ UA UG US UZ VC VN ZA ZM ZW
ARIPO: BW GH GM KE LR LS MW MZ NA RW SD SL SZ TZ UG ZM ZW
EAPO: AM AZ BY KG KZ RU TJ TM
EPO: AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
OAPI: BF BJ CF CG CI CM GA GN GQ GW KM ML MR NE SN ST TD TG
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