ANALOG TO DIGITAL CONVERTER
|Posted date||Mar 29, 2017|
|International application number||2016JP072724|
|International publication number||WO 2017029984|
|Date of international filing||Aug 3, 2016|
|Date of international publication||Feb 23, 2017|
|Title||ANALOG TO DIGITAL CONVERTER|
|Abstract||The objective of the present invention is to make it possible to perform high-speed AD conversion using a small surface area and low power consumption, by reducing the number of bits in a single-slope AD converter. To this end, according to the present invention, AD conversion is performed using a combination of: a parallel AD converter (12) which uses a plurality of comparators to compare the input potential of an analog input signal sampled using a track and hold circuit (11) with mutually different reference potentials to determine the values of a predetermined number of higher-order bits of a digital signal; and a single-slope AD converter (13) which reduces at a constant rate the input potential of the analog input signal sampled by the track and hold circuit, and converts to a digital value the time taken for the potential to equal the reference potential corresponding to the value determined by the parallel AD converter, thereby determining the remaining lower-order values of the digital signal.|
|Outline of related art and contending technology||
Converts the analog signal into a digital signal (AD converter) an analog-to-digital converter 1 of the single-slope AD converter is one (for example, Non-Patent Document 1, reference 2). The single-slope AD converter, a small area, low power consumption of the AD converter, a disadvantage in that the conversion speed is slow. For this reason, conventional, single-slope AD converter applications, such as an image sensor has been limited.
Fig. 9A is, the single-slope AD converter is a drawing showing an example, Fig. 9B is, the single-slope AD converter is a diagram showing the principle of operation. Fig. 9A a single-slope AD converter is shown, and-hold circuit 91 (track and hold: TH), the comparator 92, the lamp circuit (RAMP) 93, and time-digital converter - (time to digital converter: TDC) a 94.
91 Is-and-hold circuit, the on/off control of the clock signal CK by the analog input signal VIN is transmitted and a switch SW91, switch SW91 is transmitted via the analog input signal VIN C91 and a holding capacity. The comparator 92, the input potential Vsam and compared with the reference potential Vref, according to the comparison result output signal S91. The input potential Vsam is, the input-and-hold circuit 91 holds the analog input signal VIN and a potential in accordance with which, in the AD conversion operation is the comparison period by the lamp circuit 93 decreases at a constant speed.
The lamp circuit 93, and the switch SW92, switch SW92 via the input potential Vsam connected to the input node of a current source IS91. The lamp circuit 93, AD conversion processing time of the comparison operation, the switch SW92 is turned on and a current source IS91 is the input potential Vsam input connected to the node, the input potential Vsam reduced at a constant speed. Time - to-digital converter 94 is, the signal output from the comparator 92 indicated by the time difference S91 into a digital value, is output as the DOUT digital signal.
Fig. 9A the single-slope AD converter is shown, as shown in the example of Fig. 9B, the clock signal CK is at the high level at time T91-T92, the input of the analog input signal VIN 91 is sampled by the track-and-hold circuit. An analog input signal is VIN-and-hold circuit 91 after sampling, AD conversion processing of the T93 time from the start of the comparison operation, the analog input signal VIN is sampled in accordance with the input potential Vsam in the lamp circuit 93 is decreased at a constant speed.
AD conversion processing in the comparison operation, the input potential V in accordance with the analog input signal VINsam the lamp circuit 93 are in the begin (the comparison operation at the start of) the comparator 92 output from the signal S91 is, input potential Vsam the reference potential Vref is higher than the high level (time T93). Then, the input potential Vsam gradually decreases, the input potential Vsam and the reference voltage Vref become equal, a signal output from the comparator 92 is S91, becomes the low level (time T94).
The input potential Vsam the lamp circuit 93 are in the beginning, the input potential Vsam and the reference potential Vref is equal to, that is the comparator 92 output from the signal S91 is at a high level of time t T93-T94sam in the time - digital converter 94 into a digital value. Time tsam is, at the start of the comparison operation of the AD conversion processing is stored in the 91-and-hold the analog input signal proportional to the potential Vs according to the VIN, the output of the time - digital converter 94 the analog input signal VIN and the conversion result of the AD.
In this manner, sampled at time T91-T92 to the analog input signal VIN is converted into the digital value AD obtained by the digital signal DOUT2 is outputted as DOUT. In addition, the digital value is DOUT1, 1 before one of the sampled analog input signal VIN in the AD conversion result.
Shown in Fig. 9A the single-slope AD converter in the, time - to-digital converter 94 the number of bits of n (the output value 0 - (2n -1) ) and the time resolution Δ t and a, time tsam the maximum value of tsam (max) 2 isn expressed as Δ t. For example, 10 - bit digital signal is converted to single-slope AD converter is considered to be made, if the time resolution Δ t 100ps, time tsam (max) is and 102.4ns. AD converter of the input signal at sampling period Ts is, track period ttr time tsam (max) substantially equal to the sum of the time, the sampling frequency of the AD converter becomes equal to or less than 10MHz.
In this way, the single-slope AD converter, a small number of components of the circuit area and power consumption is small, the accuracy of the conversion times (the number of bits) in order to increase exponentially in relation to a high speed is difficult.
|IPC(International Patent Classification)|
National States: AE AG AL AM AO AT AU AZ BA BB BG BH BN BR BW BY BZ CA CH CL CN CO CR CU CZ DE DK DM DO DZ EC EE EG ES FI GB GD GE GH GM GT HN HR HU ID IL IN IR IS JP KE KG KN KP KR KZ LA LC LK LR LS LU LY MA MD ME MG MK MN MW MX MY MZ NA NG NI NO NZ OM PA PE PG PH PL PT QA RO RS RU RW SA SC SD SE SG SK SL SM ST SV SY TH TJ TM TN TR TT TZ UA UG US UZ VC VN ZA ZM ZW
ARIPO: BW GH GM KE LR LS MW MZ NA RW SD SL SZ TZ UG ZM ZW
EAPO: AM AZ BY KG KZ RU TJ TM
EPO: AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
OAPI: BF BJ CF CG CI CM GA GN GQ GW KM ML MR NE SN ST TD TG
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