Top > Search of International Patents > RADIATION-DAMAGE-COMPENSATION-CIRCUIT AND SOI-MOSFET

RADIATION-DAMAGE-COMPENSATION-CIRCUIT AND SOI-MOSFET

Foreign code F170009097
File No. (S2015-1988-N66)
Posted date May 30, 2017
Country WIPO
International application number 2016JP079797
International publication number WO 2017061544
Date of international filing Oct 6, 2016
Date of international publication Apr 13, 2017
Priority data
  • P2015-199200 (Oct 7, 2015) JP
  • 201662312804 (Mar 24, 2016) US
Title RADIATION-DAMAGE-COMPENSATION-CIRCUIT AND SOI-MOSFET
Abstract The present invention provides a radiation-damage-compensation-circuit and a SOI-MOSFET that has high radiation resistance. The SOI-MOSFET has the radiation-damage-compensation-circuit to recover the characteristics of the SOI-MOSFET after X-ray irradiation.
Outline of related art and contending technology BACKGROUND ART
Cross-Reference
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based on and claims the benefit of priority of JP Application Serial No. 2015/199200, filed on October 7, 2015 and U.S. Patent Application Serial No. 62/312,804, filed on March 24, 2016, the entire contents of which are incorporated herein by reference.
“SOI” is the same as “silicon-on-insulator”. “MOSFET” is the same as “metal-oxide-semiconductor-field-effect-transistor”. The conventional MOSFET has a structure in which a MOSFET is fabricated on a silicon-substrate, as shown in Fig. 1. The MOSFET comprises a source, gate and drain on the silicon-substrate (1). The gate (1a) consists of a channel, SiO2-layer on the channel and gate-electrode (3) on the SiO2-layer. An assembly of the source, channel and drain is called a silicon-membrane (2). An assembly of the source, gate and drain is called a transistor (1b). “SOI-MOSFET” means a MOSFET fabricated with the SOI. The conventional SOI-MOSFET has a structure in which a MOSFET is fabricated with the SOI, as shown in Fig. 2. “Depletion” means a state in which carriers such as electrons or positive holes are absent in the gate. “Partial depletion” means a state in which depletion is partial. “Complete depletion” means a state in which depletion is complete.
Positive charge is generated in the BOX when exposed with X-ray radiation. The SOI-MOSFET is less radiation-resistant against appreciable amounts of X-ray irradiation because radiation-induced positive charge in the BOX has ill effects on the transistor characteristics.
In order to solve the above problems, several methods which apply negative voltage to a bottom of the silicon-substrate, a back-gate, have been presented (Patent Literatures 1-3).
The Patent Literature 1 discloses a method for setting voltage applied to the back-gate as a function of radiation-exposition times. As shown in Fig. 2, the conventional SOI-MOSFET has a thick BOX (4) buried in a very thick silicon-substrate (1). For example, the silicon-substrate (1) is μm thick and the BOX (4) is sub-μm thick. This causes secondary problems: a very large voltage for long periods of time is required for canceling the positive charge in the BOX; discontinuous or non-constant radiation makes the performance of the SOI-transistor instable, due to overhigh or overlow voltage. The conventional SOI-MOSFET may be destroyed due to such a large voltage for long periods of time. However, the method disclosed by the Patent Literature 1 cannot resolve the above problems. The positive charge in the BOX cannot be removed with ease by applying voltage to the back-gate.
The Patent Literature 2 discloses a SOI-MOSFET that is capable of inhibiting leak-current independently with the gate-control. However, the SOI-MOSFET is essentially less resistant against radiation-exposure due to no method to cancel radiation-induced positive charge.
The Patent Literature 3 discloses the SOI-MOSFET that is capable of increasing or decreasing a threshold voltage by using high bias-substrate-coefficient on stand-by or line.
The present invention differs from the Patent Literatures 1-3 in respect to the structure and function with each other, as follows.
1) The SOI-MOSFET disclosed in the Patent Literature 1 has no system to detect the radiation-induced positive charge. Contrary, the present invention has a structure that detects a voltage threshold shift due to the radiation-induced positive charge followed by application of voltage to cancel the radiation-induced positive charge.
2) The SOI-MOSFET disclosed in the Patent Literature 2 has a well-in-well including a p-well and a n-well. Contrary, the present invention has any one of p-well or n-well but does not have the both.
3) The SOI-MOSFET disclosed in the Patent Literature 2 installs a circuit connecting the well-in-well and the back-gate in order to inhibit leak-current in the gate of the MOSFET. Contrary, the present invention mounts a circuit connecting a gate, a voltage-source and a via that penetrates the BOX to lead a buried p-well, wherein a voltage of the voltage-source is applied to the buried p-well, negative electron of the buried p-well generates, electron-tunneling to the BOX takes place, and positive charge in the BOX is canceled with the negative electron.
4) The SOI-MOSFET disclosed in the Patent-Literature 3 is able to increase a threshold voltage but is not able to detect a voltage threshold shift. Contrary, the present invention has a structure that detects a voltage threshold shift due to the radiation-induced positive charge followed by application of voltage to cancel the radiation-induced positive charge.
  • Applicant
  • ※All designated countries except for US in the data before July 2012
  • INTER-UNIVERSITY RESEARCH INSTITUTE CORPORATION HIGH ENERGY ACCELERATOR RESEARCH ORGANIZATION
  • Inventor
  • KURACHI Ikuo
  • ARAI Yasuo
  • YAMADA Miho
IPC(International Patent Classification)
Specified countries National States: AE AG AL AM AO AT AU AZ BA BB BG BH BN BR BW BY BZ CA CH CL CN CO CR CU CZ DE DJ DK DM DO DZ EC EE EG ES FI GB GD GE GH GM GT HN HR HU ID IL IN IR IS JP KE KG KN KP KR KW KZ LA LC LK LR LS LU LY MA MD ME MG MK MN MW MX MY MZ NA NG NI NO NZ OM PA PE PG PH PL PT QA RO RS RU RW SA SC SD SE SG SK SL SM ST SV SY TH TJ TM TN TR TT TZ UA UG US UZ VC VN ZA ZM ZW
ARIPO: BW GH GM KE LR LS MW MZ NA RW SD SL SZ TZ UG ZM ZW
EAPO: AM AZ BY KG KZ RU TJ TM
EPO: AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
OAPI: BF BJ CF CG CI CM GA GN GQ GW KM ML MR NE SN ST TD TG
Please contact us by E-mail if you have any interests on this patent.

PAGE TOP

close
close
close
close
close
close