Tunnel field effect transistor
|発明の名称 （英語）||Tunnel field effect transistor|
|発明の概要（英語）||The tunnel field effect transistor according to the present invention has: a channel; a source electrode connected directly or indirectly to one end of the channel; a drain electrode connected directly or indirectly to the other end of the channel; and a gate electrode for causing an electric field to act on the channel, generating a tunnel phenomenon at the source electrode-side joint part of the channel, and simultaneously generating a two-dimensional electron gas in the channel.|
1. A channel field effect transistor comprises a substrate; a core-multi-shell nano wire which comprises a channel connected to the substrate; a source electrode and a drain electrode connected to the substrate; the source electrode and the drain electrode are connected with the core-multi-shell nano line; the gate insulation film is arranged on the side of the core-multi-shell nano line; and the gate electrode and the configuration are arranged. in the brakeAn electric field acts on at least a portion of the core-multi-shell nanowire and a channel phenomenon is generated at the junction of the source electrode side of the channel, and two-dimensional electron gas is generated in the channel simultaneously.
2. The channel field effect transistor as described in item 1 of the application patent includes: the substrate having a (111) face which is doped into a first conductivity type and comprises a Group IV semiconductor, an insulating film covering the (111) surface of the substrate and having an opening portion, and the core-multi-shell nanowire configured in the (111) face of the substrate exposed in the opening portion; Around the openingThe insulating film includes III-V compound semiconductor; and the core-multi-shell nano wire comprises a first region which is connected to the (111) plane of the substrate exposed in the opening part, a first region which is connected to the first region and is doped into a second conductive type different from the first conductivity type and contains III. V compound semiconductor, barrier layer comprising a group III-V compound semiconductor having a band gap ratio larger than that of a group III-V compound semiconductor constituting said central nanowire, and a side surface coated with said center nanowire; a modulation doped layer comprising a III-V compound semiconductor larger than that of the group III-V compound semiconductor constituting said central nanowire, and semi-conducting than a group compound constituting said barrier layer. The III-V compound semiconductor of the second conductivity type, which is small in body, covers the barrier layer, and the cover layer comprises a group III-V compound semiconductor whose band gap is a band gap of a group III-V compound semiconductor constituting the central nano line and covers the modulation doped layer; and the first region is a semiconductor or a lower impurity density than the second region. It is doped into the second conductivity type, the barrier layer and the covering layer are respectively the semiconductor, or the impurity density is lower than the impurity density of the modulation doping layer and is doped into the second conductivity type, the other of the source electrode and the drain electrode is connected with the second area of the central nano wire, the gate electrode connects the (111) surface of the substrate with the central nano wire. The interface, and the first region of the central nanowire line act to generate a channel phenomenon at the junction interface and simultaneously generate two-dimensional electron gas in the first region.
3. A channel field effect transistor as described in the second item of the patent application, wherein the core-multi-shell nanowire further comprises: a first spacer layer disposed between the barrier layer and the modulation doped layer, and comprising a group III-V compound semiconductor the same as the group III-V compound semiconductor constituting the modulation doped layer; and a second spacer layer configured in the modulation doping. Layer and the covering layer between the layer and III-V compound semiconductor the same as group III-V compound semiconductor constituting the modulation doping layer and the first spacer layer; the band gap of the first spacer layer and the second spacer layer is larger than the band gap of the III-V family compound semiconductor constituting the central nano line and the III-V group of the barrier layer. The band gap of the compound semiconductor is small.
4. A channel field effect transistor as described in item 2 or 3 of the patent application, wherein the impurity density of the modulation doped layer is in the range of 10, 17 cm -10 21 cm-.
5. A switching element includes a channel field effect transistor as described in any one of items 1 to 4 of the patent application.
|参考情報 （研究プロジェクト等）||PRESTO Phase Interfaces for Highly Efficient Energy Utilization AREA|
『 Tunnel field effect transistor 』に関するお問合せ
- 国立研究開発法人科学技術振興機構（ＪＳＴ） 知的財産マネジメント推進部
- URL: http://www.jst.go.jp/chizai/
- Address: 〒102-8666 東京都千代田区四番町5-3
- TEL: 03-5214-8486
- FAX: 03-5214-8417