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Memory circuit provided with bistable circuit and non-volatile element

外国特許コード F170009249
整理番号 AF15-02EP2
掲載日 2017年10月5日
出願国 欧州特許庁(EPO)
出願番号 17151073
公報番号 3174061
公報番号 3174061
出願日 平成25年2月19日(2013.2.19)
公報発行日 平成25年2月19日(2013.2.19)
公報発行日 令和元年12月18日(2019.12.18)
国際出願番号 JP2013054052
国際公開番号 WO2013172066
国際出願日 平成25年2月19日(2013.2.19)
国際公開日 平成25年11月21日(2013.11.21)
優先権データ
  • 特願2012-114989 (2012.5.18) JP
  • 2013791129 (2013.2.19) EP
  • 2013JP054052 (2013.2.19) WO
発明の名称 (英語) Memory circuit provided with bistable circuit and non-volatile element
発明の概要(英語) A memory circuit comprising: a bistable circuit (30) configured to write data; a nonvolatile element (MTJ1, MTJ2) configured to store data written in the bistable circuit (30) in a nonvolatile manner and restore data stored in a nonvolatile manner into the bistable circuit (30) by changing a resistance value with a current flowing between one end and the other end, the nonvolatile element (MTJ1, MTJ2) having the one end connected to a node (Q, QB) in the bistable circuit (30) and the other end connected to a control line (CTRL); an FET (m7, m8) having a source and a drain connected in series to the nonvolatile element (MTJ1, MTJ2) between the node (Q, QB) and the control line (CNTL); and a control unit (85) configured to make a voltage (SR) to be applied to a gate of the FET (m7, m8) during a period to restore data stored in the nonvolatile element (MTJ1, MTJ2) in a nonvolatile manner into the bistable circuit (30) lower than a supply voltage to be applied to the bistable circuit (30) during a period to write data into and read data from the bistable circuit (30) in a volatile manner.
従来技術、競合技術の概要(英語) BACKGROUND ART
In a known memory device, data written in a bistable circuit of a SRAM (Static Ramdom Access Memory) is stored into a ferromagnetic tunnel junction element (MTJ) in a nonvolatile manner, to cut off the power supply to the bistable circuit. After that, when the bistable circuit is turned on, the data is restored into the bistable circuit from the MTJ (see Patent Document 1, for example). Power consumption can be reduced by using this memory device in a microprocessor, a system-on-chip, a microcontroller, an FPGA (Field Programmable Gate Array), a CMOS (Complementary Metal Oxide Semiconductor) logic, or the like.
特許請求の範囲(英語) [claim1]
1. A memory circuit comprising:
a bistable circuit (30) configured to write data;
a nonvolatile element (MTJ1, MTJ2) configured to store data written in the bistable circuit (30) in a nonvolatile manner by changing a resistance value with a current flowing between one end and the other end and restore data stored in a nonvolatile manner into the bistable circuit (30), the nonvolatile element (MTJ1, MTJ2) having the one end connected to a node (Q, QB) in the bistable circuit (30) and the other end connected to a control line (CTRL);
an FET (m7, m8) having a source and a drain connected in series to the nonvolatile element (MTJ1, MTJ2) between the node (Q, QB) and the control line (CTRL); and characterized in that the memory circuit further comprises:
a control unit (85) configured to make a highest voltage (SR) to be applied to a gate of the FET (m7, m8) during a period to restore data stored in the nonvolatile element (MTJ1, MTJ2) in a nonvolatile manner into the bistable circuit (30) lower than a voltage of a node being at a high level in the bistable circuit (30) during a period to write data into and read data from the bistable circuit (30) in a volatile manner.

[claim2]
2. The memory circuit according to claim 1, wherein the control unit (85) is further configured to make the highest voltage (SR) to be applied to the gate during a period to store data written in the bistable circuit (30) into the nonvolatile element (MTJ1,MTJ2) in a nonvolatile manner lower than the voltage of the node being at a high level in the bistable circuit (30) during the period to write data into and read data from the bistable circuit (30) in a volatile manner.

[claim3]
3. The memory circuit according to claim 1 or 2, wherein the control unit (85) is further configured to make the highest voltage to be applied to the control line (CTRL) during a period to store data written in the bistable circuit (30) into the nonvolatile element (MTJ1, MTJ2) in a nonvolatile manner lower than the voltage of the node being at a high level in the bistable circuit (30) during the period to write data into and read data from the bistable circuit (30) in a volatile manner.
  • 出願人(英語)
  • JAPAN SCIENCE AND TECHNOLOGY AGENCY
  • 発明者(英語)
  • SHUTO, Yusuke
  • YAMAMOTO, Shuichiro
  • SUGAHARA, Satoshi
国際特許分類(IPC)
指定国 Contracting States: AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
参考情報 (研究プロジェクト等) CREST Research of Innovative Material and Process for Creation of Next-generation Electronics Devices AREA
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