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Memory circuit provided with bistable circuit and non-volatile element

Foreign code F170009249
File No. AF15-02EP2
Posted date Oct 5, 2017
Country EPO
Application number 17151073
Gazette No. 3174061
Gazette No. 3174061
Date of filing Feb 19, 2013
Gazette Date Feb 19, 2013
Gazette Date Dec 18, 2019
International application number JP2013054052
International publication number WO2013172066
Date of international filing Feb 19, 2013
Date of international publication Nov 21, 2013
Priority data
  • P2012-114989 (May 18, 2012) JP
  • 2013791129 (Feb 19, 2013) EP
  • 2013JP054052 (Feb 19, 2013) WO
Title Memory circuit provided with bistable circuit and non-volatile element
Abstract A memory circuit comprising: a bistable circuit (30) configured to write data; a nonvolatile element (MTJ1, MTJ2) configured to store data written in the bistable circuit (30) in a nonvolatile manner and restore data stored in a nonvolatile manner into the bistable circuit (30) by changing a resistance value with a current flowing between one end and the other end, the nonvolatile element (MTJ1, MTJ2) having the one end connected to a node (Q, QB) in the bistable circuit (30) and the other end connected to a control line (CTRL); an FET (m7, m8) having a source and a drain connected in series to the nonvolatile element (MTJ1, MTJ2) between the node (Q, QB) and the control line (CNTL); and a control unit (85) configured to make a voltage (SR) to be applied to a gate of the FET (m7, m8) during a period to restore data stored in the nonvolatile element (MTJ1, MTJ2) in a nonvolatile manner into the bistable circuit (30) lower than a supply voltage to be applied to the bistable circuit (30) during a period to write data into and read data from the bistable circuit (30) in a volatile manner.
Outline of related art and contending technology BACKGROUND ART
In a known memory device, data written in a bistable circuit of a SRAM (Static Ramdom Access Memory) is stored into a ferromagnetic tunnel junction element (MTJ) in a nonvolatile manner, to cut off the power supply to the bistable circuit. After that, when the bistable circuit is turned on, the data is restored into the bistable circuit from the MTJ (see Patent Document 1, for example). Power consumption can be reduced by using this memory device in a microprocessor, a system-on-chip, a microcontroller, an FPGA (Field Programmable Gate Array), a CMOS (Complementary Metal Oxide Semiconductor) logic, or the like.
Scope of claims [claim1]
1. A memory circuit comprising:
a bistable circuit (30) configured to write data;
a nonvolatile element (MTJ1, MTJ2) configured to store data written in the bistable circuit (30) in a nonvolatile manner by changing a resistance value with a current flowing between one end and the other end and restore data stored in a nonvolatile manner into the bistable circuit (30), the nonvolatile element (MTJ1, MTJ2) having the one end connected to a node (Q, QB) in the bistable circuit (30) and the other end connected to a control line (CTRL);
an FET (m7, m8) having a source and a drain connected in series to the nonvolatile element (MTJ1, MTJ2) between the node (Q, QB) and the control line (CTRL); and characterized in that the memory circuit further comprises:
a control unit (85) configured to make a highest voltage (SR) to be applied to a gate of the FET (m7, m8) during a period to restore data stored in the nonvolatile element (MTJ1, MTJ2) in a nonvolatile manner into the bistable circuit (30) lower than a voltage of a node being at a high level in the bistable circuit (30) during a period to write data into and read data from the bistable circuit (30) in a volatile manner.

[claim2]
2. The memory circuit according to claim 1, wherein the control unit (85) is further configured to make the highest voltage (SR) to be applied to the gate during a period to store data written in the bistable circuit (30) into the nonvolatile element (MTJ1,MTJ2) in a nonvolatile manner lower than the voltage of the node being at a high level in the bistable circuit (30) during the period to write data into and read data from the bistable circuit (30) in a volatile manner.

[claim3]
3. The memory circuit according to claim 1 or 2, wherein the control unit (85) is further configured to make the highest voltage to be applied to the control line (CTRL) during a period to store data written in the bistable circuit (30) into the nonvolatile element (MTJ1, MTJ2) in a nonvolatile manner lower than the voltage of the node being at a high level in the bistable circuit (30) during the period to write data into and read data from the bistable circuit (30) in a volatile manner.
  • Applicant
  • JAPAN SCIENCE AND TECHNOLOGY AGENCY
  • Inventor
  • SHUTO, Yusuke
  • YAMAMOTO, Shuichiro
  • SUGAHARA, Satoshi
IPC(International Patent Classification)
Specified countries Contracting States: AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
Reference ( R and D project ) CREST Research of Innovative Material and Process for Creation of Next-generation Electronics Devices AREA
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