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NEURAL NETWORK CIRCUIT AND NEURAL NETWORK INTEGRATED CIRCUIT NEW

外国特許コード F180009314
整理番号 (S2016-0777-N0)
掲載日 2018年1月24日
出願国 世界知的所有権機関(WIPO)
国際出願番号 2017JP018836
国際公開番号 WO 2017200088
国際出願日 平成29年5月19日(2017.5.19)
国際公開日 平成29年11月23日(2017.11.23)
優先権データ
  • 特願2016-100694 (2016.5.19) JP
  • 特願2016-222275 (2016.11.15) JP
発明の名称 (英語) NEURAL NETWORK CIRCUIT AND NEURAL NETWORK INTEGRATED CIRCUIT NEW
発明の概要(英語) The purpose of the present invention is to provide an efficient and versatile neural network circuit while significantly reducing the size and cost of the circuit. The neural network circuit comprises: memory cells 1 which are provided in the same number as that of pieces of input data I, and each of which performs a multiplication function by which each piece of input data I consisting of one bit is multiplied by a weighting coefficient W; and a majority determination circuit 2 for performing an addition/application function by which the multiplication results of the memory cells 1 are added up, an activation function is applied to the addition result, and a piece of one-bit output data is outputted. Each of the memory cells stores the weighting coefficient, which is either "1" or "0," or "NC," whereby the memory cell outputs "1" when the piece of input data I is equal to the value stored therein, "0" when the value of the input data I is not equal to the value stored therein, or "NC" when "NC" is stored therein. The majority determination circuit 2 outputs "1" or "0" on the basis of the total number of memory cells 1 outputting "1" and the total number of memory cells 1 outputting "0."
特許請求の範囲(英語) [claim1]
1. 1 - Bit input data in which each of the weighting factor a multiplier multiplying the plurality of first function 1 and the circuit section, wherein each of said first circuit part in the 1 and the multiplication results are added to a result of the activation function is applied to the 1 - bit output data output by the adder/2 applied to the first circuit unit for implementing the functions, the neural network comprises a circuit, wherein each of said first circuit part each comprise 1, '1' or '0' is a weighting factor, the pre-set or predetermined value of a storage unit that stores, in the storage unit stores the weighting factor in a case where the input data and the weighting factor is equal to the value of the input data to the input timing of the timing corresponding to '1' outputs, wherein the weighting factor different from the value of the input data in the event that the input timing of input data at a timing corresponding to '0' and outputs, in the storage unit is a predetermined value and the stored data if the input timing of input data at a timing corresponding to the output unit outputs a predetermined value, and, wherein the first circuit portion is 2, '1' at the first output and the total number of circuit unit 1, '0' 1 wherein the first output and the total number of the circuit section, based on the difference between, wherein said output data as '1' or '0' and the output of the neural network circuit.
[claim2]
2. A neural network circuit according to claim 1, wherein the first circuit portion is 2, '1' of claim 1 wherein the first circuit output and the total number of '0' of claim 1 wherein the first output circuit to the total number of the difference is equal to or greater than a predetermined threshold value '1' according to the output data to be output as a, wherein the difference is less than the threshold value in the case of a '0' according to the output data is output as a feature from a neural network circuit.
[claim3]
3. A neural network circuit according to claim 2, equal to the number of the plurality of input data 1 wherein said first circuit part, the number of input data wherein the number of protrusions 1 and the second circuit, wherein the circuit is modeled by the neural network based on the brain function has been set in advance and the number of neural network circuit.
[claim4]
4. Wherein the input data is input to each of the first circuit such that the number 1 n (n is a natural number of 2 or more) in the neural network circuit according to claim 3 m (m is a natural number of 2 or more) are provided, each neural network circuit to one of said n parallel input data inputted to the common and, wherein each of said neural network outputs the output data output from each neural network characterized in that the integrated circuit.
[claim5]
5. Wherein m and n is equal to the integrated circuit according to claim 4 neural networks are connected to a plurality of series, wherein one of the neural network output data output from the integrated circuit, the neural network which is connected to the integrated circuit immediately after the other neural network in an integrated circuit wherein the input data and output from a neural network characterized in that the integrated circuit.
[claim6]
6. A neural network integrated circuit according to claim 4 k (k is a natural number of 2 or more) are provided, each of said neural network with respect to the integrated circuit and one of said n parallel input data is input in common, wherein each of said neural network integrated circuit from one of said m parallel outputs the output data to the neural network and each of the integrated circuit.
[claim7]
7. A plurality of the integrated circuit and a neural network according to claim 4, wherein each of said neural network integrated circuit array are connected to each other and each neural network integrated circuit wherein the input data and output data in the unit switches, correspond to the function of the brain switch unit switching operation in advance and the switch unit is set, and a neural network which is characterized in that it comprises an integrated circuit.
[claim8]
8. A neural network circuit according to claim 2, said weighting coefficient, the neural network circuit is modelled by a brain functions and previously set in correspondence with, the memory unit, said weighting coefficients are stored and the output part of the second output pixel 1 and a storage unit storing, corresponding to the functions of the brain with a pre-set to a predetermined value and said output section of the second output pixel stored in the storage unit and a 2, and composed, wherein the output section includes, wherein the first storage unit 1 and a weighting factor output from said input data when said value coincides with the input timing of input data at a timing corresponding to '1' and outputs, according to the output value of the weighting coefficient and the input data is different from the input timing of input data at a timing corresponding to '0' outputs, wherein the first predetermined value 2 is output from the storage unit in the event that the input timing of input data at a timing corresponding to the predetermined value and outputs the neural network circuit.
[claim9]
9. A neural network circuit according to claim 8, the adder applying function/is added as a function, corresponding to the function of the brain and set in advance as a function of the brain to each neuron tends to tend to even integer representing the coefficient, the absolute value of greater than or equal to 0 and less than the number of said input data is trend coefficients, each multiplication result with respect to the case where the result of the addition of further be added, the absolute value of the tendency of any second 1 equal to the number of the circuit section has been input and the divided coefficient trend, the trend coefficient inputted into the first circuit unit 1, according to the predetermined value, the result of the addition of the multiplication result for each of the tendency of the first coefficient of the addition result to the further output circuit section 2, 2 wherein the first circuit section includes, wherein the tendency of the first coefficient further result of the addition circuit 1 for each value from the total adding when positive or 0 '1' and the output as output data, when the total value is negative when the '0' to the output as the output data of the neural network and the circuit.
[claim10]
10. A neural network circuit according to claim 8, correspond to the function of the brain with a pre-set as a function of the brain and the trend tendency to each neuron is an integer denoting a coefficient, the absolute value is greater than or equal to 0 and less than or equal to the number of input data wherein the trend tendency of coefficients further comprising a coefficient storage section, wherein the first circuit portion is 2, wherein each of said first circuit section 1 to the result of the addition of the multiplication result from a predetermined value and the trend in accordance with the total value is the sum of the coefficient when the positive or 0 '1' and the output as output data, the total value is negative when a '0' to the output as the output data of the neural network and the circuit.
[claim11]
11. A neural network circuit according to claim 8, wherein the input data of one and the number, according to the output data, 1 wherein the first storage unit, wherein the first storage unit 2, 2 1 wherein the first circuit unit and the second number of each of the circuit portion, wherein the brain functions previously set in correspondence with the number of not less than two, the weighting factor and the predetermined value corresponding to the function of the brain with each of the pre-set value and, wherein each of said first output unit is circuit unit 1, according to the output data of each of said weighted coefficients corresponding to the respective input data and the result of the multiplication based on the outputs according to the output data in each of the task, wherein each of said first circuit portion is 2, the predetermined value when the pre-set in a value, '1' in the multiplication result from the total number of '0' is a value obtained by subtracting a total number of the multiplication result is equal to or less than the threshold, '1' and the output as output data, wherein the predetermined value is set in advance in the case where the value, wherein when said value obtained by subtracting a smaller than the threshold value, '0' to the output as the output data of the neural network and the circuit.
[claim12]
12. A neural network circuit according to claim 8, according to the output data and the second one and the number of circuit unit 2 respectively, wherein the input data, 1 wherein the first storage unit, the first storage unit and the second 2 1 the number of each of the circuit, wherein the brain functions has been set in advance corresponding to two or more numbers, each of the weighting factor and a predetermined value and the value corresponding to the brain functional, wherein each of said first circuit portion is 1, each said input data corresponding to the input of the each of the input data and the weighting factor and the multiplication result on the basis of the output of the input data in each of the task, wherein the first circuit portion is 2, the predetermined value set in the preset value in the case where, '1' The method according to the result of the multiplication from the total number of '0' is a value obtained by subtracting the total number of the multiplication result is equal to or greater than the threshold value, '1' and the output as output data, wherein the predetermined value is set in advance in the case where the value, wherein when the value obtained by subtracting a is below the threshold value, '0' according to the output data is output as a feature from a neural network circuit.
[claim13]
13. A neural network circuit according to claim 11, neural network circuit according to claim 12, provided, one of the input data is input to the neural network according to claim 11 each output data outputted from the circuit, and each of the input data in the neural network circuit according to claim 12 and, according to claim 12 neural network circuit from the output data of the neural network characterized in that the integrated circuit.
[claim14]
14. A neural network in an integrated circuit according to claim 13, neural network circuit according to claim 11 neural network according to claim 12 and the circuitry further comprising a register, the register units, each of the output data output from the neural network circuit according to claim 11 one buffered by the reference clock, said neural network circuit according to claim 12 neural network according to claim 12 as each of the input data in the output circuit and the integrated circuit output from a neural network.
[claim15]
15. A plurality of integrated circuits according to claim 13 neural network connected in series, one of the one of the neural network from the integrated circuit to the output of the data, the subsequent linear neural network to the integrated circuit and one of said input data output from a neural network characterized in that the integrated circuit.
[claim16]
16. A plurality of integrated circuits according to claim 13 neural network, a neural network according to claim 13 with respect to each of the plurality of integrated circuits is input in common to one of the types and input data, the plurality of separate from the integrated circuit according to claim 13 neural network and wherein the output data are output one by one a neural network which is characterized in that the integrated circuit.
  • 出願人(英語)
  • ※2012年7月以前掲載分については米国以外のすべての指定国
  • HOKKAIDO UNIVERSITY
  • 発明者(英語)
  • MOTOMURA MASATO
国際特許分類(IPC)
指定国 (WO2017200088)
National States: AE AG AL AM AO AT AU AZ BA BB BG BH BN BR BW BY BZ CA CH CL CN CO CR CU CZ DE DJ DK DM DO DZ EC EE EG ES FI GB GD GE GH GM GT HN HR HU ID IL IN IR IS JP KE KG KH KN KP KR KW KZ LA LC LK LR LS LU LY MA MD ME MG MK MN MW MX MY MZ NA NG NI NO NZ OM PA PE PG PH PL PT QA RO RS RU RW SA SC SD SE SG SK SL SM ST SV SY TH TJ TM TN TR TT TZ UA UG US UZ VC VN ZA ZM ZW
ARIPO: BW GH GM KE LR LS MW MZ NA RW SD SL SZ TZ UG ZM ZW
EAPO: AM AZ BY KG KZ RU TJ TM
EPO: AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
OAPI: BF BJ CF CG CI CM GA GN GQ GW KM ML MR NE SN ST TD TG
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