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COPPER FILM FORMATION DEVICE, COPPER FILM FORMATION METHOD, COPPER WIRING FORMATION METHOD, AND COPPER WIRING meetings

Foreign code F180009337
File No. S2016-0471-C0
Posted date Mar 13, 2018
Country WIPO
International application number 2017JP005390
International publication number WO 2017145876
Date of international filing Feb 15, 2017
Date of international publication Aug 31, 2017
Priority data
  • P2016-035760 (Feb 26, 2016) JP
Title COPPER FILM FORMATION DEVICE, COPPER FILM FORMATION METHOD, COPPER WIRING FORMATION METHOD, AND COPPER WIRING meetings
Abstract The present invention addresses the problem of inexpensively obtaining a semiconductor device that uses copper wiring. A crucible (CuI vapor generating means) (30) is provided on the lower side of a film formation chamber (10) at a location facing a substrate (100). A raw material heating heater (CuI vapor generating means) (31) and a thermocouple (32) are fitted to the crucible (30), and the temperature of the crucible (30) can be measured and controlled. The crucible 30 is filled with particles that serve as the raw material for forming the copper film. The particles are formed from CuI. A CuI vapor is generated by heating the crucible (30) in a vacuum, and the substrate (100) is exposed to the CuI vapor. By setting the temperature Tsub of the substrate (100) to approximately 300°C, it is possible to deposit Cu only on a conductive metal material without depositing any on an insulator.
Outline of related art and contending technology BACKGROUND ART
In recent years, LSI (semiconductor integrated circuit) as the structure of the wiring. A plurality of wiring layers laminated through an interlayer insulating layer on the multilayer wiring structure is widely used. Here, in particular for lower resistance of wiring is required, as the material constituting the wiring layer, a low electrical resistivity of copper is used. As the method of forming copper wiring, in general, dry etching of the copper itself is used in the damascene method is not performed. Fig. 7 is, in the copper damascene method in the case of forming a multilayer wiring step will be described. Here, in the multilayer wiring, the wiring layer 1 on the lower side 2 and the upper side of the wiring layer and the vias and connected. The first wiring layer 1, vias, each of the first wiring layer 2 mainly made of copper and a copper wiring, and each of these desired shape is formed so as to be connected.
As shown in Fig. 7A, in this case, a semiconductor (Si) in a wafer-shaped, SiO2 and the like in the interlayer insulating layer to 70, in Fig. 1 which extends in a direction perpendicular to the wiring layer 71 is formed. 1 In the first wiring layer 71 may be made of copper and formed. Next, as shown in Fig. 7B, these interlayer insulating layer over the form 72. Then, as shown in Fig. 7C, the first wiring layer 1 on the interlayer insulating layer 72 to 71, the first wiring layer 1 so as to expose the surface of the 71, 72A (recess) by dry etching to form an opening (recessed portion forming step). Here, the shape of the opening 72A, 71 and the second wiring layer 1 formed on the connection between the first wiring layer 2 is used corresponding to the shape of the via.
Then, as shown in Fig. 7D, opening 72A including the inside of the barrier metal layer thinly over the entire formation (undercoat metal layer) 73 (the foundation metal layer forming step). The barrier metal layer 73 composed of TiN for example. Then, as shown in Fig. 7E, so as to bury the opening 72A, formed on the entire surface 300 sufficiently thicker than the copper layer (copper layer forming step). Then, CMP (chemical mechanical polishing) to the copper layer 300 by performing, on the interlayer insulating layer 72 the copper layer 300 and the barrier metal layer 73 is removed (CMP step). In the CMP, copper and the chemical reaction and mechanical polishing in order to perform at the same time, the copper layer 300 are removed the interlayer insulating layer 72 is removed in a condition in which the CMP can be performed. In addition, the barrier metal layer 73 is thin enough, be removed at the time of this CMP, as a result, as shown in Fig. 7F, the copper layer 72A only in opening 300 and the barrier metal layer 73 can be remained, the copper layer 300 and the barrier metal layer 73 other than this are all removed. Therefore, the opening 72A of the copper layer 300 and the barrier metal layer 73 (mainly the copper layer 300) and the via 74. As shown in Fig. 7F, the surface becomes flat at this time. Incidentally, the barrier metal layer 73 as described above, the electrolytic plating copper layer 300 is formed using, in this case serves as a seed layer is used, or the seed layer and the barrier metal layer and the barrier metal layer of the laminated structure 73 described above can be made.
Then, as shown in Fig. 7 g, again on the flat surface of the interlayer insulating layer (insulating layer forming step) 75 is formed, as shown in Fig. 7H, in the interlayer insulating layer 75, 72A of the aperture (recess) is greater than the groove 75A is formed (concave portion forming step). The shape of the groove 75A, corresponding to the shape of the first wiring layer 2, the groove 75A (the first wiring layer 2) 1 in the same manner as the first wiring layer 71 extending in the vertical direction of the figure. Then, as shown in Fig. 7I, the barrier metal layer 73 is formed in the same manner as Fig. 7D (the foundation metal layer forming step) and then, as shown in Fig. 7J, in the same manner as Fig. 7E so as to bury the groove 75A, sufficiently thicker than the copper layer 300 formed on the entire surface (copper layer forming step). Thereafter, similar to the above CMP can be performed by (CMP step), as shown in Fig. 7K, the copper layer 75A remaining only in the groove 300 and the barrier metal layer 73 and the second wiring layer 2 76. Incidentally, the first wiring layer 1 for 71, 2 having the same structure as the first wiring layer 76, can be a method for manufacturing.
In the above manufacturing method, the vias 74, 2 such as the first wiring layer 76 for forming copper wiring on the lower layer wiring, (1) the interlayer insulation layer and the recessed portion forming step, (2) the base metal layer forming step, (3) the copper layer forming step, (4) the step of CMP, the steps of, in forming the vias 74 above the first wiring layer 1 71 as a lower layer wiring, the first wiring layer 76 are formed by the vias 2 74 as a lower layer wiring as described above, is repeated. In this way, the formation of a via interconnect layer is formed are performed for each method is called single damascene method. On the other hand, the second wiring layer 1 on the first and second openings corresponding to vias in the wiring layer 2 corresponding to the continuous groove formed in the interlayer insulating layer and then, these openings and grooves forming the copper layer is embedded at the same time, by performing CMP after the first via and a wiring layer 2 is formed at a time is performed by a dual damascene method.
Dry etching is performed using the fine processing of copper, aluminum or the like having a high resistivity than copper compared to, it is difficult in general. In the above manufacturing method, the processing of the copper (the copper layer 300) is performed only by CMP, dry etch is required, to form a fine wiring by using copper on such manufacturing method is particularly preferred. In addition, immediately after the CMP step (Fig. 7F, Fig. 7K) is in, since the surface is planarized, a plurality of stacked vias and a wiring layer on the multilayer wiring structure is formed, the production method described above is particularly preferred. Fig. 7 in one wiring layer structure according to 2 (the first 1 wiring layer 71 to the structure 76 from the first wiring layer 2) has been described a method of manufacturing, by repeating the steps described above can be produced than the laminate structure.
Here, the wiring resistance is sufficiently low, and in order to improve the reliability of the wiring, the copper layer forming step (Fig. 7E, Fig. 7J) in, after the vias 74, 76 and 300 the first wiring layer 2 a copper layer, the opening 72A and the groove 75A is filled into the sufficiently dense in necessary. Such a request is satisfied a copper layer 300 as a film formation method, an electrolytic plating (for example Patent Document 1) is mainly used. In addition, CVD (chemical vapor deposition) method may be used (for example Patent Document 2) are provided. In addition, compared with the method of these poor filling property even in the case of using a sputtering method, heat treatment is performed for about 400°C after the film formation by causing reflow, the copper layer 300 can be formed in the same manner as has been known (for example Patent Document 3).
Scope of claims (In Japanese)[請求項1]
基板上に銅を成膜する銅の成膜装置であって、
前記基板を減圧雰囲気下で内部に収容する成膜チャンバと、
前記基板を加熱する基板加熱手段と、
CuI(ヨウ化銅(I))蒸気を前記成膜チャンバ中で前記基板に照射するCuI蒸気発生手段と、
を具備することを特徴とする銅の成膜装置。
[請求項2]
前記基板加熱手段において、前記基板の温度を250~350℃の範囲とすることを特徴とする請求項1に記載の銅の成膜装置。
[請求項3]
前記CuI蒸気発生手段は、固体状のCuI(ヨウ化銅(I))を含む原料を加熱して気化させて前記CuI蒸気を生成することを特徴とする請求項1又は2に記載の銅の成膜装置。
[請求項4]
前記CuI蒸気発生手段において、前記原料を300~400℃の温度に加熱することを特徴とする請求項3に記載の銅の成膜装置。
[請求項5]
前記成膜チャンバ内の圧力は1×10-3Torr以下とされることを特徴とする請求項1から請求項4までのいずれか1項に記載の銅の成膜装置。
[請求項6]
前記成膜チャンバの内面は絶縁体で構成され、かつその温度が200℃以上とされたことを特徴とする請求項1から請求項5までのいずれか1項に記載の銅の成膜装置。
[請求項7]
基板における少なくとも部分的に導電性とされた表面上に銅を成膜する銅の成膜方法であって、
前記基板を加熱し、減圧雰囲気下でCuI(ヨウ化銅(I))蒸気を前記表面に照射することを特徴とする銅の成膜方法。
[請求項8]
前記基板の温度を250~350℃とすることを特徴とする請求項7に記載の銅の成膜方法。
[請求項9]
CuI(ヨウ化銅(I))を含む固体の原料を減圧雰囲気下で300~400℃の温度に加熱することによって前記CuI蒸気を生成することを特徴とする請求項7又は8に記載の銅の成膜方法。
[請求項10]
前記原料及び前記基板の雰囲気の圧力を1×10-3Torr以下とすることを特徴とする請求項7から請求項9までのいずれか1項に記載の銅の成膜方法。
[請求項11]
絶縁層中に埋め込まれた銅配線を形成する銅配線形成方法であって、
前記銅配線に対応する凹部を前記絶縁層に形成する凹部形成工程と、
前記凹部の底面において露出する下地金属層の上において、請求項7から請求項10までのいずれか1項に記載の銅の成膜方法によって選択的に銅を成膜する銅層形成工程と、
を具備することを特徴とする銅配線形成方法。
[請求項12]
前記凹部形成工程と前記銅層形成工程の間に、前記下地金属層を前記底面上に形成する下地金属層形成工程を具備することを特徴とする請求項11に記載の銅配線形成方法。
[請求項13]
前記銅配線は前記絶縁層の下の下層配線と接続するように形成され、前記下地金属層を前記下層配線の表面に形成することを特徴とする請求項11に記載の銅配線形成方法。
[請求項14]
基板上に形成された絶縁層中に埋め込まれて形成された銅配線であって、前記基板の表面に対して垂直方向に延伸する柱状結晶構造を具備することを特徴とする銅配線。
[請求項15]
前記柱状結晶構造の延伸する方向は銅の(111)方向であることを特徴とする請求項14に記載の銅配線。
[請求項16]
前記銅配線の(111)配向の配向度は90%以上であることを特徴とする請求項15に記載の銅配線。
補正された請求の範囲(条約第19条)
[
2017年6月22日
(
22.06.2017
) 国際事務局受理 ]

[1]
基板上に銅を成膜する銅の成膜装置であって、
前記基板を減圧雰囲気下で内部に収容する成膜チャンバと、
前記基板を加熱する基板加熱手段と、
CuI(ヨウ化銅(I))蒸気を前記成膜チャンバ中で前記基板に照射するCuI蒸気発生手段と、
を具備することを特徴とする銅の成膜装置。
[2]
前記基板加熱手段において、前記基板の温度を250~350℃の範囲とすることを特徴とする請求項1に記載の銅の成膜装置。
[3]
前記CuI蒸気発生手段は、固体状のCuI(ヨウ化銅(I))を含む原料を加熱して気化させて前記CuI蒸気を生成することを特徴とする請求項1又は2に記載の銅の成膜装置。
[4]
前記CuI蒸気発生手段において、前記原料を300~400℃の温度に加熱することを特徴とする請求項3に記載の銅の成膜装置。
[5]
前記成膜チャンバ内の圧力は1×10-3Torr以下とされることを特徴とする請求項1から請求項4までのいずれか1項に記載の銅の成膜装置。
[6]
前記成膜チャンバの内面は絶縁体で構成され、かつその温度が200℃以上とされたことを特徴とする請求項1から請求項5までのいずれか1項に記載の銅の成膜装置。
[7]
基板における少なくとも部分的に導電性とされた表面上に銅を成膜する銅の成膜方法であって、
前記基板を加熱し、減圧雰囲気下でCuI(ヨウ化銅(I))蒸気を前記表面に照射することを特徴とする銅の成膜方法。
[8]
前記基板の温度を250~350℃とすることを特徴とする請求項7に記載の銅の成膜方法。
[9]
CuI(ヨウ化銅(I))を含む固体の原料を減圧雰囲気下で300~400℃の温度に加熱することによって前記CuI蒸気を生成することを特徴とする請求項7又は8に記載の銅の成膜方法。
[10]
前記原料及び前記基板の雰囲気の圧力を1×10-3Torr以下とすることを特徴とする請求項7から請求項9までのいずれか1項に記載の銅の成膜方法。
[11]
絶縁層中に埋め込まれた銅配線を形成する銅配線形成方法であって、
前記銅配線に対応する凹部を前記絶縁層に形成する凹部形成工程と、
前記凹部の底面において露出する下地金属層の上において、請求項7から請求項10までのいずれか1項に記載の銅の成膜方法によって選択的に銅を成膜する銅層形成工程と、
を具備することを特徴とする銅配線形成方法。
[12]
前記凹部形成工程と前記銅層形成工程の間に、前記下地金属層を前記底面上に形成する下地金属層形成工程を具備することを特徴とする請求項11に記載の銅配線形成方法。
[13]
前記銅配線は前記絶縁層の下の下層配線と接続するように形成され、前記下地金属層を前記下層配線の表面に形成することを特徴とする請求項11に記載の銅配線形成方法。
[14]
[削除]
[15]
[削除]
[16]
[削除]
  • Applicant
  • ※All designated countries except for US in the data before July 2012
  • IBARAKI UNIVERSITY
  • Inventor
  • YAMAUCHI, Satoshi
IPC(International Patent Classification)
Specified countries National States: AE AG AL AM AO AT AU AZ BA BB BG BH BN BR BW BY BZ CA CH CL CN CO CR CU CZ DE DJ DK DM DO DZ EC EE EG ES FI GB GD GE GH GM GT HN HR HU ID IL IN IR IS KE KG KH KN KP KR KW KZ LA LC LK LR LS LU LY MA MD ME MG MK MN MW MX MY MZ NA NG NI NO NZ OM PA PE PG PH PL PT QA RO RS RU RW SA SC SD SE SG SK SL SM ST SV SY TH TJ TM TN TR TT TZ UA UG US UZ VC VN ZA ZM ZW
ARIPO: BW GH GM KE LR LS MW MZ NA RW SD SL SZ TZ UG ZM ZW
EAPO: AM AZ BY KG KZ RU TJ TM
EPO: AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
OAPI: BF BJ CF CG CI CM GA GN GQ GW KM ML MR NE SN ST TD TG
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