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SEMICONDUCTOR DEVICE

Foreign code F180009401
File No. (AF47P001)
Posted date Apr 20, 2018
Country WIPO
International application number 2017JP006776
International publication number WO 2018042707
Date of international filing Feb 23, 2017
Date of international publication Mar 8, 2018
Priority data
  • P2016-170939 (Sep 1, 2016) JP
Title SEMICONDUCTOR DEVICE
Abstract According to the present invention, a contact layer comprising a material with an electron concentration of less than 1 × 1022 cm-3 is directly provided on a surface of a semiconductor crystal of an n-type conductivity with a band gap at room temperature of not more than 1.2 eV. In this way, the wave function penetration from the contact layer side to the semiconductor surface side is suppressed, and, as a result, the generation of a barrier φB due to the Fermi level pinning phenomenon can be suppressed, and a lower resistivity and more highly ohmic contact can be achieved.
Outline of related art and contending technology BACKGROUND ART
Is a semiconductor device which is essential for the electrode, ohmic contact with the semiconductor surface is achieved, it is necessary to reduce the contact resistance as much as possible. For this purpose, the following two ways are usually taken. The first method, the impurity concentration of the semiconductor side is raised, electrons in the tunnel effect through out the semiconductor side is constructed for a situation. The second method is, as the material of the electrode, in ohmic contact with the semiconductor material can be selected as a material having a work function of the present invention.
However, the conductivity-type semiconductor crystal in the case of n, even if in theory an ohmic contact with the metal having a work function should be selected, in many cases, due to the Schottky contact is known. This phenomenon, a so-called 'fermi level pinning' are believed to be due.
According to the Schottky theory, n-type semiconductor and a metal contact surface (bonding surface) of the Schottky barrier φB is, the work function φM and the n-type semiconductor electron affinity φX and the difference (φM -φX) to be given. However, in most cases, the theoretical and the actual Schottky energy barrier due to the Schottky barrier does not match. Such a phenomenon, if in the Fermi level of the 'pinned' due to the effect in order to appear, are referred to as a fermi level pinning. The fermi level pinning is, as well as Si, Ge or the like of the semiconductor most of the connection between a metal and a phenomenon seen. Here, φM, φχ, φB and V of each unit.
N-type semiconductor and the electrode material at the interface between the contact resistivity ρC is, the Schottky barrier φB and the bonding interface area per unit volume of the donor concentration ND and, the relationship of the following formula 1. It should be noted that, in the formula of λ is constant.
That is, n-type semiconductor and the electrode material forms an interface with the ohmic contact, the contact resistivity ρC in order to reduce, the Schottky barrier φB to reduce the height, the bonding interface region of the donor concentration ND should be increased.
However, the bonding interface region of the donor concentration ND in order to increase the solid solubility limit at thermal equilibrium state and that, close to the solid solubility limit concentration is usually increased and, more may not be high. On the other hand, as described above, especially in the case of n-type semiconductor, the fermi level pinning phenomenon, the Schottky barrier φB to the desired degree cannot be sufficiently low.
Further, with a miniaturization of the semiconductor device becomes smaller and the area of contact, as would be readily understood from the above equation 1, the contact area and contact resistance Rc is the actual S ρC /Sand, the same as the ρC with miniaturization even if the rapid rise and, the semiconductor element to effectively improve the performance of the original to prevent. That is, the drain electrode of the semiconductor element is miniaturized, the total resistance for the contact resistance between the source electrode in order not to increase the ratio, ρC itself can be reduced strongly demanded.
Therefore, as the above-described n-type semiconductor junction interface between the electrode material in a high donor concentration ND semiconductor layer is provided also in an attempt to achieve an ohmic contact have been made (Patent Document 1: JP-2012-124483 JP Patent Document 2: Japanese Patent Laid-Open No. 2014-41987 Japanese).
For example, to Patent Document 2, n-type Ge and the metal electrode from the fermi level pinning phenomenon between the n-type Ge metal barrier to electrons flowing in the direction φB is generated, as a result of this contact resistance becomes high and is known, n-type Ge and the metal between the electrodes, the electron concentration (carrier concentration) n-type Ge layer to increase the depletion layer is made at an extremely narrow, tunneling of electrons, it is expected that ohmic contact have been developed to the effect that, by inexpensive processes, electrode layer and the n-Ge layer to reduce contact resistance of the n+ -type Ge semiconductor layer and the ohmic contact forming method for the purpose of providing a structure, n-type Ge and the metal layer between the layer, the electron concentration 1019 cm-3 a thickness of 2nm or more greater than or equal to n+ -type Ge layer is formed of an ohmic contact structure characterized in that the disclosed invention.
Scope of claims (In Japanese)[請求項1]
室温におけるバンドギャップが1.2eV以下のn型導電型を有する半導体結晶の表面に、電子濃度が1×1022cm-3未満の材料から成るコンタクト層が直接設けられているコンタクト構造を備えている、半導体装置。

[請求項2]
前記半導体結晶は、Si、Ge、もしくはSiとGeの化合物(SixGey)の何れかである、請求項1に記載の半導体装置。

[請求項3]
前記半導体結晶はGeであり、前記コンタクト層はGd、Y、Ho、Er、Ybの何れかのゲルマニウム化物もしくはBiを主成分とする材料から成る、請求項1に記載の半導体装置。

[請求項4]
前記半導体結晶はSiであり、前記コンタクト層はBiを主成分とする材料から成る、請求項1に記載の半導体装置。

[請求項5]
前記半導体結晶の表面領域のドナー濃度が1×1018cm-3以下である、請求項1に記載の半導体装置。

[請求項6]
前記コンタクト層の上に金属層を備えている、請求項1~5の何れか1項に記載の半導体装置。

[請求項7]
前記半導体装置は、前記半導体結晶がSiもしくはGeである、nチャネルMOSFETである、請求項1~6の何れか1項に記載の半導体装置。
  • Applicant
  • ※All designated countries except for US in the data before July 2012
  • JAPAN SCIENCE AND TECHNOLOGY AGENCY
  • Inventor
  • TORIUMI Akira
  • NISHIMURA Tomonori
IPC(International Patent Classification)
Reference ( R and D project ) CREST Development of Atomic or Molecular Two-Dimensional Functional Films and Creation of Fundamental Technologies for Their Applications AREA
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