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NEURON CIRCUIT, SYSTEM, AND SWITCH CIRCUIT NEW

外国特許コード F180009434
整理番号 (AF47P002)
掲載日 2018年7月23日
出願国 世界知的所有権機関(WIPO)
国際出願番号 2017JP025932
国際公開番号 WO 2018100790
国際出願日 平成29年7月18日(2017.7.18)
国際公開日 平成30年6月7日(2018.6.7)
優先権データ
  • 特願2016-233444 (2016.11.30) JP
発明の名称 (英語) NEURON CIRCUIT, SYSTEM, AND SWITCH CIRCUIT NEW
発明の概要(英語) A neuron circuit comprising: an input terminal to which spike signals are input in chronological order; a first switch element with one end connected to the input terminal and the other end connected to an intermediate node, the first switch element maintaining a high-resistance state even when receiving a single spike signal and changing a resistance state from the high-resistance state to a low-resistance state when receiving a plurality of spike signals during a first period; a feedback circuit connected to the intermediate node, the feedback circuit setting the input terminal to a prescribed level when the first switch element changes to the low-resistance state; and a second switch element connected in series with the first switch element between the input terminal and the intermediate node, the second switch element maintaining the low-resistance state even when the input terminal receives one or a plurality of spike signals and changing to the high-resistance state when the input terminal is set to the prescribed level.
特許請求の範囲(英語) [claim1]
1. In which a spike signal is input in time series and an input terminal, with one end connected to the input terminal, the other end is connected to the intermediate node, a spike in a single input signal is a high-resistance state is maintained, a plurality of spikes within a time period of the first input signal 1 and its resistance value is lower than the high-resistance state and a low-resistance state 1 and the second switch element, connected to said intermediate node, wherein the first switching element 1 and the low-resistance state to the input terminal and a feedback circuit and the predetermined level, the input terminal of said first intermediate node between the switch element 1 connected in series, wherein a plurality of spikes or 1 input terminal of the input signal while maintaining the low-resistance state, to the input terminal becomes the predetermined level and the second high-resistance state and a plurality of switch elements 2, comprising a neuron circuit.
[claim2]
2. Wherein the intermediate node and the reference potential terminal and a load connected between the neuron circuit of according to claim 1 hEGF.
[claim3]
3. Wherein the predetermined level is at a high level of according to claim 2 neuron circuit.
[claim4]
4. Wherein the first switch element is 1, and the other end and one end connected between, on one end to the other end within a time period 2 and the second voltage applied to the internal-state quantities obtained by averaging the first high-resistance state and lower than the threshold value 1 and, wherein the amount of the internal state of the low-resistance state when the first threshold is greater than 2 and 3 resistive elements of any one of claims from the claim 1 neuron circuit.
[claim5]
5. Wherein the resistance body, and a metallic phase and greater than a predetermined temperature, wherein the insulating phase and is lower than predetermined temperature, wherein the amount of the internal state, wherein the first temperature within a time period 2 to the other end of the voltage applied to said one end of the neuron circuit of according to claim 4 in RMS.
[claim6]
6. Wherein the first switch element is 1, the one end and connected to said other end, the internal-state quantities 1 is greater than the first threshold and the high-resistance state, wherein the first internal-state quantities to 2 higher than the threshold value and the low-resistance state when the resistance body comprises, T time0in said internal-state-quantity S (T0) is, on one end and the other end of the voltage V10, V10said internal-state quantities to the influence of the f (V10), and said internal-state quantities to the relaxation time τdecwhen claim 1 in any one of claims 3 from of the neuron circuit.
[claim7]
7. Wherein the resistance body, and a metallic phase and greater than a predetermined temperature, wherein the insulating phase and is lower than predetermined temperature, when a constant f A (V10) =AxV102according to claim 6 in of the neuron circuit.
[claim8]
8. Claim 1 vanadium oxide from the resistance body is any one of claims 7 wherein the neuron circuit.
[claim9]
9. Wherein the intermediate node between the input terminal of said first switch element and the second 2 switch 1 are connected in series, a spike in a single input signal is a high-resistance state is maintained, in the period 3 of the first plurality of said spike signal input 3 and the low-resistance state the first switch element of claim 1 comprising any one of claims 7 from the neuron circuit.
[claim10]
10. 3 The high-resistance state of the switch element is a resistance value of the first high-resistance state of the switch element 1 is higher than the value of the resistance, wherein the first low-resistance state of the switch 3 is the resistance value of the first high-resistance state of the switch element 1 is lower than the resistance value of the neuron circuit of according to claim 9.
[claim11]
11. Claim 1 10 from any one of the neuron circuit and one of the preceding claims, wherein the neuron synapse circuit and a circuit of the memory, the system comprising.
[claim12]
12. Receiving an input signal and an input terminal, and an output terminal, and the one end connected to the input terminal, and the other end connected to the output terminal, said one end and the other end connected to, the internal-state quantities is greater than the first threshold 1 becomes the high resistance state, said internal-state quantities to 2 when the first threshold is greater than the high-resistance state and the low resistance state resistance value than the resistance body and, comprising a switch element, comprising, time T0in said internal-state-quantity S (T0) is, on one end and the other end of the voltage V10, V10is internal-state quantities to the influence of the f (V10), and said internal-state quantities to the relaxation time τdecwhen and, wherein the variation of the input signal is shorter than the relaxation time is the period of the switch circuit.
[claim13]
13. A plurality of spikes signal and said input signal, said a plurality of spikes signal interval is shorter than the relaxation time of the switch circuit according to claim 12.
[claim14]
14. Wherein the resistance body, and a metallic phase and greater than a predetermined temperature, wherein the insulating phase and is lower than predetermined temperature, when a constant f A (V10) =AxV102claims 12 or 13 described in the switch circuit.
  • 出願人(英語)
  • ※2012年7月以前掲載分については米国以外のすべての指定国
  • JAPAN SCIENCE AND TECHNOLOGY AGENCY
  • 発明者(英語)
  • Toriumi Akira
国際特許分類(IPC)
指定国 (WO2018100790)
National States: AE AG AL AM AO AT AU AZ BA BB BG BH BN BR BW BY BZ CA CH CL CN CO CR CU CZ DE DJ DK DM DO DZ EC EE EG ES FI GB GD GE GH GM GT HN HR HU ID IL IN IR IS JO JP KE KG KH KN KP KR KW KZ LA LC LK LR LS LU LY MA MD ME MG MK MN MW MX MY MZ NA NG NI NO NZ OM PA PE PG PH PL PT QA RO RS RU RW SA SC SD SE SG SK SL SM ST SV SY TH TJ TM TN TR TT TZ UA UG US UZ VC VN ZA ZM ZW
ARIPO: BW GH GM KE LR LS MW MZ NA RW SD SL SZ TZ UG ZM ZW
EAPO: AM AZ BY KG KZ RU TJ TM
EPO: AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
OAPI: BF BJ CF CG CI CM GA GN GQ GW KM ML MR NE SN ST TD TG
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