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FIXED-WEIGHTING-CODE LEARNING DEVICE NEW

外国特許コード F180009562
整理番号 (S2017-0527-N0)
掲載日 2018年11月5日
出願国 世界知的所有権機関(WIPO)
国際出願番号 2018JP004786
国際公開番号 WO 2018168293
国際出願日 平成30年2月13日(2018.2.13)
国際公開日 平成30年9月20日(2018.9.20)
優先権データ
  • 特願2017-048421 (2017.3.14) JP
発明の名称 (英語) FIXED-WEIGHTING-CODE LEARNING DEVICE NEW
発明の概要(英語) A neural network circuit is provided with which it is possible to significantly reduce the area occupied by the connection unit of an FC-type neural network circuit. An analog-type neural network circuit SS constituting a learning device having a self-learning function and corresponding to a brain function, wherein the neural network SS comprises: a plurality (n) of input-side neurons NR; a plurality (m, and including cases when n=m) of output-side neurons NR; (n × m) connection units CN each connecting one input-side neuron NR and one output-side neuron NR; and a self-learning control unit C, the (n × m) connection units CN being constituted from connection units CN corresponding to only the positive weighting function as a brain function, and connection units CN corresponding to only the negative weighting function as the brain function.
従来技術、競合技術の概要(英語) BACKGROUND ART
In recent years, the functions of the brain of the person using a deep neural network circuit (a so-called deep learning function) associated with a learning function of the research and development has been carried out.At this time, the neural network circuit in the case in specific implementation, a digital circuit is used and a case where an analog circuit is used and a case where.Here, the former has a high processing capability and a large-scale hardware is needed and the power consumption is increased, for example used in the data center or the like.While the latter, the processing capability is inferior as compared with the case of the digital circuit is used, as a hardware configuration and minimized to reduce the power consumption can be expected, for example a terminal connected to the data center or the like is often used for a device.Then, as for the latter prior art, the following technique disclosed in Patent Document 1 and the like.
Patent Document 1 is, configured by analog circuits (that is an analog type) neural network circuit, the output side of all the neurons of the input side and all of the neurons, corresponding to the respective weight of the resistance value by a connecting portion having the one-to-one connection, a so-called deep learning of the neural network circuit is coupled to all disclosed (FC(Full Connection) ) type.Weighting is in this case, the neural network circuit should correspond to the weighting and corresponding to the brain function, disclosed in Patent Document 1 is provided with a neural network circuit, the resistance value of each connection section is constituted by a variable resistance element correspond to each of the weight.FC-type neural network circuit such as, for example in the form of a neural network in the vicinity of the other coupled circuit, a large scale neural network than can be used as part of the circuit, itself further improves the processing capability, reduction in circuit scale (area) is desired.
  • 出願人(英語)
  • ※2012年7月以前掲載分については米国以外のすべての指定国
  • NATIONAL UNIVERSITY CORPORATION HOKKAIDO UNIVERSITY
  • 発明者(英語)
  • ASAI TETSUYA
国際特許分類(IPC)
指定国 National States: AE AG AL AM AO AT AU AZ BA BB BG BH BN BR BW BY BZ CA CH CL CN CO CR CU CZ DE DJ DK DM DO DZ EC EE EG ES FI GB GD GE GH GM GT HN HR HU ID IL IN IR IS JO JP KE KG KH KN KP KR KW KZ LA LC LK LR LS LU LY MA MD ME MG MK MN MW MX MY MZ NA NG NI NO NZ OM PA PE PG PH PL PT QA RO RS RU RW SA SC SD SE SG SK SL SM ST SV SY TH TJ TM TN TR TT TZ UA UG US UZ VC VN ZA ZM ZW
ARIPO: BW GH GM KE LR LS MW MZ NA RW SD SL SZ TZ UG ZM ZW
EAPO: AM AZ BY KG KZ RU TJ TM
EPO: AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
OAPI: BF BJ CF CG CI CM GA GN GQ GW KM ML MR NE SN ST TD TG
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