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DATA PROCESSING DEVICE NEW

外国特許コード F190009704
整理番号 (S2017-0666-N0)
掲載日 2019年1月23日
出願国 世界知的所有権機関(WIPO)
国際出願番号 2018JP018169
国際公開番号 WO 2018207883
国際出願日 平成30年5月10日(2018.5.10)
国際公開日 平成30年11月15日(2018.11.15)
優先権データ
  • 特願2017-096061 (2017.5.12) JP
発明の名称 (英語) DATA PROCESSING DEVICE NEW
発明の概要(英語) A data processing device (1) in which multiple basic units (10) are interconnected. Each basic unit (10) includes an intra-unit register unit (11). The basic unit (10) in question reads data from the intra-unit register unit (11) and performs a calculation using the data, and then caries out a pipeline execution wherein, in each execution cycle, a register group corresponding to the execution cycle among intra-unit register units (21) included in the later-stage basic units is updated.
従来技術、競合技術の概要(英語) BACKGROUND ART
A plurality of operation units and interconnected by a network of two-dimensional systolic array type accelerator having a structure known as the prior art (Patent Document 1).
Patent Document 1 disclosed in the conventional accelerator, the amount of wiring is mounted on the multi time LSI(Large Scale Integrated Circuit) FPGA(Field Programmable Gate Array) and likely become a problem.FPGA and the circuit scale of the LSI becomes larger, an increase in signal delay of the wiring is to be made.
In addition, Patent Document 1 is an accelerator, as a result of each arithmetic unit is computing its own bypass the input of the self-loops is provided.Each computing result of the arithmetic unit itself for use in calculating the kno.
Self-loop structure arithmetic is required for the operation that corresponds to the accumulator, for calculating is pipelined to improve the performance of the operation method cannot be applied.The non-pipeline processing of the operation becomes a factor of reducing efficiency in the use.
For example, Patent Document 1 is an accelerator, an arithmetic unit composed of a plurality of blocks and, if the circuit configuration of the pipeline processing is possible at the considered.However, the result of the operation of the next execution cycle when executing an input operation, data transfer between each block because it is necessary, pipeline processing cannot be performed.Therefore, the usage rate of the arithmetic circuit 1 and to the extent that the number, the use efficiency is lowered.
  • 出願人(英語)
  • ※2012年7月以前掲載分については米国以外のすべての指定国
  • NATIONAL UNIVERSITY CORPORATION NARA INSTITUTE OF SCIENCE AND TECHNOLOGY
  • 発明者(英語)
  • NAKASHIMA, Yasuhiko
国際特許分類(IPC)
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