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TUNNELING FIELD EFFECT TRANSISTOR NEW

外国特許コード F190009876
整理番号 AF41-02WO
掲載日 2019年7月29日
出願国 世界知的所有権機関(WIPO)
国際出願番号 2018JP043787
国際公開番号 WO 2019107411
国際出願日 平成30年11月28日(2018.11.28)
国際公開日 令和元年6月6日(2019.6.6)
優先権データ
  • 201762591798 (2017.11.29) US
発明の名称 (英語) TUNNELING FIELD EFFECT TRANSISTOR NEW
発明の概要(英語) A tunneling field effect transistor according to an embodiment of the present invention includes: a first semiconductor layer of a first conductive type; a second semiconductor layer of a second conductive type, the second conductive layer forming, in a first region, a hetero-junction with the first semiconductor layer; a gate insulating layer covering the second semiconductor layer in the first region; a gate electrode layer that covers the gate insulating layer; a first electrode layer electrically connected to the first semiconductor layer; a second electrode layer electrically connected to the second semiconductor layer; and a first insulating layer which in a second region is sandwiched between the first semiconductor layer and the second semiconductor layer, the second region being adjacent to the second electrode layer side with respect to the first region.
従来技術、競合技術の概要(英語) BACKGROUND ART
To reduce the power consumption of electronic devices, large-scale integrated circuit MOS-type field effect transistor (MOSFET) constituting the low voltage operation is strongly demanded. In recent years, a quantum tunneling phenomenon is used as a new operation principle of a tunnel field effect transistor (hereinafter, referred to as' TFET ') is attracting attention. By using the quantum tunneling phenomenon, a statistical distribution and the electron temperature does not follow the operation, that is, the sweep voltage width of a small sharp ON/OFF operation becomes possible. A tunnel field effect transistor is, for example, Japanese Patent Laid-Open 1-9 as disclosed in, various configurations have been studied.
  • 出願人(英語)
  • ※2012年7月以前掲載分については米国以外のすべての指定国
  • JAPAN SCIENCE AND TECHNOLOGY AGENCY
  • 発明者(英語)
  • KATO Kimihiko
  • TAKAGI Shinichi
  • TAKENAKA Mitsuru
  • TABATA Hitoshi
  • MATSUI Hiroaki
国際特許分類(IPC)
指定国 National States: AE AG AL AM AO AT AU AZ BA BB BG BH BN BR BW BY BZ CA CH CL CN CO CR CU CZ DE DJ DK DM DO DZ EC EE EG ES FI GB GD GE GH GM GT HN HR HU ID IL IN IR IS JO JP KE KG KH KN KP KR KW KZ LA LC LK LR LS LU LY MA MD ME MG MK MN MW MX MY MZ NA NG NI NO NZ OM PA PE PG PH PL PT QA RO RS RU RW SA SC SD SE SG SK SL SM ST SV SY TH TJ TM TN TR TT TZ UA UG US UZ VC VN ZA ZM ZW
ARIPO: BW GH GM KE LR LS MW MZ NA RW SD SL SZ TZ UG ZM ZW
EAPO: AM AZ BY KG KZ RU TJ TM
EPO: AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
OAPI: BF BJ CF CG CI CM GA GN GQ GW KM ML MR NE SN ST TD TG
参考情報 (研究プロジェクト等) CREST Innovative nano-electronics through interdisciplinary collaboration among material, device and system layers AREA
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