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NEURAL ELECTRONIC CIRCUIT NEW

外国特許コード F190009966
整理番号 (S2018-0359-N0)
掲載日 2019年10月25日
出願国 世界知的所有権機関(WIPO)
国際出願番号 2019JP002455
国際公開番号 WO 2019155910
国際出願日 平成31年1月25日(2019.1.25)
国際公開日 令和元年8月15日(2019.8.15)
優先権データ
  • 特願2018-019252 (2018.2.6) JP
発明の名称 (英語) NEURAL ELECTRONIC CIRCUIT NEW
発明の概要(英語) Provided is a neural electronic circuit for realizing a neural network capable of dealing with multiple-bit data while reducing the size of the electronic circuit. The neural electronic circuit is provided with: storage units (MC) that each store a logarithmic weighting coefficient, which represents, in multiple bits, a value resulting from logarithmizing a weighting coefficient corresponding to input data to be inputted, and that outputs the logarithmic weighting coefficient on a bit-by-bit basis; first electronic circuit units (Pe) that each output a multiplication result of the input data and the weighting coefficient; and a second electronic circuit units (Act) that each realize an addition/application function of adding the multiplication results, applying an activation function to the addition result, and outputting output data. In the neural electronic circuit, logarithmic input data, which represents, in multiple bits, a value resulting from logarithmizing the input data, is received on a bit-by-bit basis, logarithmic addition is calculated by adding the logarithmic input data and the logarithmic weighting coefficient outputted from the storage unit, a multiplication result is calculated by linearizing the logarithmic addition result, and the logarithmized output data is outputted.
従来技術、競合技術の概要(英語) BACKGROUND ART
In recent years, a model brain function of a person, a so-called neural network research and development is being performed for a circuit. At this time, the conventional neural network circuit may be, for example using a floating point or fixed point product-sum operation in many cases be implemented using, in this case, the calculation cost is increased, the problem of high processing load.
In recent years, the input data and the weighting coefficient for each of the bits 1, a so-called 'binary neural network circuit' algorithms have been proposed. Here, the binary neural network circuit according to the algorithm as the prior art literature, for example the following Non-Patent Document 1 and Non-Patent Document 2 and the like.
  • 出願人(英語)
  • ※2012年7月以前掲載分については米国以外のすべての指定国
  • HOKKAIDO UNIVERSITY
  • 発明者(英語)
  • TAKAMAEDA Shinya
  • UEYOSHI Kodai
  • MOTOMURA Masato
国際特許分類(IPC)
指定国 National States: AE AG AL AM AO AT AU AZ BA BB BG BH BN BR BW BY BZ CA CH CL CN CO CR CU CZ DE DJ DK DM DO DZ EC EE EG ES FI GB GD GE GH GM GT HN HR HU ID IL IN IR IS JO JP KE KG KH KN KP KR KW KZ LA LC LK LR LS LU LY MA MD ME MG MK MN MW MX MY MZ NA NG NI NO NZ OM PA PE PG PH PL PT QA RO RS RU RW SA SC SD SE SG SK SL SM ST SV SY TH TJ TM TN TR TT TZ UA UG US UZ VC VN ZA ZM ZW
ARIPO: BW GH GM KE LR LS MW MZ NA RW SD SL SZ TZ UG ZM ZW
EAPO: AM AZ BY KG KZ RU TJ TM
EPO: AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR
OAPI: BF BJ CF CG CI CM GA GN GQ GW KM ML MR NE SN ST TD TG
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